Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “module” throughout the claim language.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5 and 19 are rejected under 35 U.S.C. 102 (a)(1)as being anticipated by Zhang et al. (US Pub. No. 2023/0140104 A1).
As to claim 1, Zhang shows a display driving circuit (Figs. 1 and 2 and paras. 34 – 37), comprising: a first scan (gate) driving circuit 20/21 (Fig. 1 and para. 35), the first scan driving circuit comprising: a plurality of first shift registers 211 arranged in cascade (Fig. 2 and para. 37), the first shift register comprising a first register input terminal IN and a first register output terminal OUT (Fig. 2 and para. 38); and at least one first cascade control module (including elements T1, T2 and T4, Fig. 2 and paras. 38), one of the at least one first cascade control module comprising a first cascade control unit (i.e. controlling operations of subsequent shift registers, Figs. 2 – 4 and paras. 37 – 45), wherein the first cascade control unit is connected between two of the first shift registers (Fig. 2), the two of the first shift registers comprise a current-stage first shift register and a next-stage first shift register (Fig. 2 and para. 38), the current-stage first shift register comprise a current-stage first register output terminal (Fig. 2 and para. 38), the next-stage first shift register comprise a next-stage first register input terminal (Fig. 2 and para. 38); and the first cascade control unit is configured to control a connection state between the current-stage first register output terminal and the next-stage first register input terminal (Fig. 2 and para. 38); and the one of the at least one first cascade control module further comprising a signal transfer unit (i.e. T2/T4, for example, Fig. 2 and para. 38), wherein a control terminal of the signal transfer unit is applied a transfer control signal (i.e. U2D/D2U, Fig. 2 and paras. paras. 37 – 45), an input terminal of the signal transfer unit is applied a start control signal (i.e. OUT of previous shift register, Fig. 2 and paras. 38 – 45), and an output terminal of the signal transfer unit is electrically connected to the next-stage first register input terminal (i.e. IN of subsequent shift register, Fig. 2 and paras. 38 – 45); and the signal transfer unit is configured to transmit the start control signal to the next-stage first register input terminal in response to the transfer control signal (Fig. 2 and paras. 38 – 45).
As to claim 3, Zhang shows that the start control signal comprises a pulse signal (Figs. 2 and 3 and paras. 38 – 45), the control terminal of the signal transfer unit is electrically connected to the input terminal of the signal transfer unit (Fig. 2), and the transfer control signal is reused as the start control signal (Figs. 2 and 3 and paras. 38 – 45).
As to claim 5, Zhang shows that the current-stage first shift register and the next-stage first shift register are respectively an ith-stage first shift register and an (i+a)th-stage first shift register, where i and a are both positive integers (Fig. 2 and para. 38), wherein in a case where the ith-stage first shift register outputs a cutoff potential of an ith-stage scan signal and the (i+a)th-stage first shift register outputs a turn-on potential of an (i+a)th- stage scan signal, during a phase when the ith-stage first shift register outputs the cutoff potential of the ith-stage scan signal, the first cascade control unit is configured to cut off a connection between the ith-stage first shift register and the (i+a)th-stage first shift register (Figs. 2 – 4 and paras. 38 – 45), and the signal transfer unit is configured to transmit the start control signal to a first register input terminal of the (i+a)th-stage first shift register in response to the transfer control signal (Figs. 2 – 4 and paras. 38 – 45); and in a case where the ith-stage first shift register outputs a turn-on potential of the ith-stage scan signal and the (i+a)th-stage first shift register outputs a cutoff potential of the (i+a)th-stage scan signal, during a phase when the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal, the first cascade control unit is configured to cut off the connection between the ith-stage first shift register and the (i+a)th-stage first shift register (Figs. 2 – 4 and paras. 38 – 45), and the signal transfer unit is configured to be turned off in response to the transfer control signal (Figs. 2 – 4 and paras. 38 – 45).
As to claim 19, Zhang shows a plurality of pixel driver circuits 10 (Fig. 1 and para. 35) and a plurality of first scan lines 11 (Fig. 1 and para. 47), wherein the plurality of pixel driver circuits are arranged in an array (Fig. 1), and each row of pixel driver circuits is electrically connected to at least one of the plurality of first scan lines (Fig. 1 and para. 47); and first register output terminals in the first scan driving circuit are electrically connected to the first scan lines (Figs. 1 and 2 and paras. 38 and 47); the pixel driver circuit comprising: a driving module M1 (Fig. 10 and para. 74), a data writing module M6 (Fig. 10 and para. 75), a threshold compensation module M3 (Fig. 10 and para. 75), and a light emission control module M6/M7 (Fig. 10 and para. 75), wherein the driving module is connected between the light emission control module and a light-emitting device (Fig. 10), and the driving module is configured to generate a driving current (Fig. 10 and paras. 74 and 75); the data writing module is electrically connected to a first terminal of the driving module (Fig. 10), and the data writing module is configured to transmit a data voltage to the driving module (Fig. 10 and paras. 74 and 75); the threshold compensation module is connected between a control terminal and a second terminal of the driving module (Fig. 10), and the threshold compensation module is configured to compensate for a threshold voltage of the driving module (Fig. 10 and paras. 74 and 75); and the first scan line is electrically connected to control terminals of threshold compensation modules in a corresponding row of pixel driver circuits (Fig. 10 and paras. 74 ad 75); and the pixel driver circuit further comprises a first reset module M4 electrically connected to the control terminal of the driving module (Fig. 10 and paras. 74 and 75), the first reset module being configured to reset the control terminal of the driving module (Fig. 10 and paras. 74 and 75); and the display driving circuit further comprises: a plurality of second scan lines (Fig. 1 and para. 47), the second scan lines being electrically connected to control terminals of first reset modules in corresponding rows of pixel driver circuits (Figs. 1 and 10 and paras. 74 and 75), wherein first register output terminals in the first scan driving circuit are electrically connected to the second scan lines (Figs. 1, 7 and 10), wherein a second scan line connected to a jth row of pixel driver circuits is electrically connected to a jth-stage first register output terminal (Figs. 1, 7 and 10), and a first scan line connected to the jth row of pixel driver circuits is electrically connected to a (j+b)th-stage first register output terminal, wherein j and b are both positive integers (Figs. 1, 7 and 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Pak et al (US Pub. No. 2009/0262058 A1).
As to claim 2, Zhang does not show that the start control signal comprises a reference signal having fixed potential; and the signal transfer unit is configured to transmit the reference signal to the next-stage first register input terminal in response to the transfer control signal.
Pak shows that a start control signal STV comprises a reference signal having fixed potential (Figs. 5 and 6 and para. 64); and that a signal transfer unit ST1/ST2 is configured to transmit the reference signal to a subsequent stage first register input terminal in response to a transfer control signal (i.e. SC1/SC2, Figs. 5 and 6 and paras. 61 – 68).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the teachings of Zhang with those of Pak because designing the system in this way allows the device to operate each stage in sequence (para. 67).
As to claim 4, Zhang shows that the first cascade control unit comprises a first switch sub-unit T2 (Fig. 2 and para. 38), a control terminal of the first switch sub-unit being applied a first switch signal (i.e. U2D, Fig. 2 and para. 38), a first terminal of the first switch sub-unit being electrically connected to the current-stage first register output terminal (Fig. 2 and para. 38), and a second terminal of the first switch sub-unit being electrically connected to the next-stage first register input terminal (Fig. 2 and para. 38); and the start control signal comprises: a pulse signal, and the signal transfer unit is configured to transmit the pulse signal to the next-stage first register input terminal in response to the transfer control signal (Figs. 2 – 4 and paras. 38 – 45).
Zhang does not show that the transfer control signal and the first switch signal are opposite in phase.
Pak shows that a transfer control signal and a first switch signal are opposite in phase (Figs. 5 and 6 and para. 64).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the teachings of Zhang with those of Pak because designing the system in this way allows the device to operate each stage in sequence (para. 67).
Allowable Subject Matter
Claims 6 – 18 and 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically, claim 6 recites “…the first cascade control unit is connected between an mth-stage first shift register and an (m+a)th-stage first shift register, wherein m and a are both positive integers; and the (m+a)th-stage first shift register is a next-stage first shift register corresponding to the mth-stage first shift register; and the first scan driving circuit further comprises at least one second cascade control module, one of the at least one second cascade control module comprising a second cascade control unit, the second cascade control unit being connected between a kth-stage first shift register and a (k+a)th-stage first shift register, wherein k is a positive integer less than m, and the (k+a)th-stage first shift register is a next-stage first shift register corresponding to the kth-stage first shift register.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claims 7 – 13 contain allowable subject matter at least by virtue of their dependence on claim 6.
Claim 14 recites “… the at least one first cascade control module comprises a plurality of first cascade control modules, each of the first cascade control modules being disposed between two corresponding first shift registers among at least part of the first shift registers; and the first scan driving circuit further comprises a plurality of second shift registers arranged in cascade, wherein at least part of the second shift registers are arranged respectively corresponding to the at least part of the first shift registers; and the second shift register comprises a second register input terminal and a second register output terminal, wherein an input terminal of the signal transfer unit is electrically connected to a corresponding second register output terminal among the at least part of the second shift registers, and a corresponding start control signal is output to the input terminal of the corresponding signal transfer unit through the second register output terminal among the at least part of the second shift registers.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claims 15 – 18 contain allowable subject matter at least by virtue of their dependence on claim 14.
Claim 20 recites “… the signal transfer unit comprises a first transistor, wherein a gate of the first transistor is applied the transfer control signal, a first electrode of the first transistor is applied the start control signal, and a second electrode of the first transistor is electrically connected to a corresponding next-stage first register input terminal; the first cascade control unit comprises a first switch sub-unit, the first switch sub-unit comprising a second transistor, wherein a gate of the second transistor is applied a first switch signal, a first electrode of the second transistor is electrically connected to a corresponding current-stage first register output terminal, and a second electrode of the second transistor is electrically connected to a corresponding next-stage first register input terminal; and the first cascade control unit further comprises a second switch sub-unit, the second switch sub-unit comprising a third transistor, wherein a gate of the third transistor is applied a second switch signal, a first electrode of the third transistor is applied an auxiliary turn-off signal, and a second electrode of the third transistor is electrically connected to a corresponding next-stage first register input terminal.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
CONCLUSION
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/CARL ADAMS/Examiner, Art Unit 2627
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