DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 2 and 19 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (U.S. PG Pub 2017/0059897).
Regarding Claim 1, Xu et al. teach a light-emitting substrate, comprising:
a plurality (Figures 5 and 6, Elements IC1 and IC2. Paragraph 67) of driver chips (Figures 1 - 6, Element IC. Paragraph 28); and
a plurality of device groups (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89), wherein
a device group (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) in the plurality of device groups (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) includes at least one light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89), and the at least one light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) is electrically connected to a driver chip (Figures 1 - 6, Element IC. Paragraph 28) in the plurality (Figures 5 and 6, Elements IC1 and IC2. Paragraph 67) of driver chips (Figures 1 - 6, Element IC. Paragraph 28); and
the driver chip (Figures 1 - 6, Element IC. Paragraph 28) includes at least one output pin (Figures 1 - 6, Element Vo. Paragraph 30) and a first functional pin (Figures 1 - 6, Element Vtest. Paragraph 33); a light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) in the device group (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) is electrically connected to an output pin (Figures 1 - 6, Element Vo. Paragraph 30); the first functional pin (Figures 1 - 6, Element Vtest. Paragraph 33) is capable of receiving a test signal, and the driver chip (Figures 1 - 6, Element IC. Paragraph 28) is configured to output, according to the test signal, a test current to the at least one light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) for driving the at least one light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) to emit light.
Regarding Claim 2, Xu et al. teach the light-emitting substrate according to claim 1 (See Above), further comprising a conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89), wherein the conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89) includes a second voltage line (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89); and
a terminal of the light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) is electrically connected to the output pin (Figures 1 - 6, Element Vo. Paragraph 30), and another terminal of the light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) is electrically connected to the second voltage line (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89); and the second voltage line (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89) is configured to provide an operating voltage for the light-emitting unit (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89).
Regarding Claim 19, Xu et al. teach the light-emitting substrate according to claim 1 (See Above), wherein the at least one output pin (Figures 1 - 6, Element Vo. Paragraph 30) includes a plurality of output pins (Figures 1 - 6, Elements Vo1 and Vo2. Paragraph 30), and the plurality of output pins (Figures 1 - 6, Elements Vo1 and Vo2. Paragraph 30) are arranged along an extending direction of an edge of the driver chip (Figures 1 - 6, Element IC. Paragraph 28).
Regarding Claim 20, Xu et al. teach a display apparatus (Paragraph 89), comprising the light-emitting substrate according to claim 1 (See Above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 – 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (U.S. PG Pub 2017/0059897) in view of Yang et al. (U.S. PG Pub 2011/0018888).
Regarding Claim 3, Xu et al. teach the light-emitting substrate according to claim 1 (See Above), wherein the driver chip (Figures 1 - 6, Element IC. Paragraph 28) further includes a second functional pin (Figures 1 - 6, Element Vtest2. Paragraph 33) electrically connected to the first functional pin (Figures 1 - 6, Element Vtest. Paragraph 33).
Xu et al. is silent with regards to among driver chips connected to the plurality of device groups, a second functional pin of a former-stage driver chip is electrically connected to a first functional pin of a latter-stage driver chip through a first external connection line.
Yang et al. teach among driver chips (Figure 4, Elements 120. Paragraph 25) connected to the plurality of device groups, a second functional pin (Figure 4, Elements Fault. Paragraph 25) of a former-stage driver chip (Figure 4, Elements 120. Paragraph 25) is electrically connected to a first functional pin (Figure 4, Elements Ena. Paragraph 25) of a latter-stage driver chip (Figure 4, Elements 120. Paragraph 25) through a first external connection line (Seen in Figure 4).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. with the teachings of the addressing method of Yang et al. The motivation to modify the teachings of Xu et al. with the teaching of Yang et al. is to provide an addressing method for a plurality of chips, as taught by Yang et al. (Paragraph 12).
Regarding Claim 4, Xu et al. in view of Yang et al. teach the light-emitting substrate according to claim 3 (See Above). Xu et al. teach further comprising a conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89), wherein the conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89) includes a test signal line electrically connected to a first functional pin (Figures 1 - 6, Element Vtest. Paragraph 33) of a first-stage driver chip (Figures 1 - 6, Element IC. Paragraph 28), and the test signal line is configured to provide the test signal for the first-stage driver chip (Figures 1 - 6, Element IC. Paragraph 28).
Regarding Claim 5, Xu et al. in view of Yang et al. teach the light-emitting substrate according to claim 3 (See Above). Xu et al. teach wherein the driver chip (Figures 1 - 6, Element IC. Paragraph 28) has a first edge and a second edge that are parallel to each other (Seen in Figures 2a – 6).
Xu et al. is silent with regards to one of the first functional pin and the second functional pin is close to the first edge, and another one thereof is close to the second edge; and the second functional pin is electrically connected to the first functional pin through a first connection line.
Yang et al. teach one of the first functional pin (Figure 4, Elements Ena. Paragraph 25) and the second functional pin (Figure 4, Elements Fault. Paragraph 25) is close to the first edge (Seen n Figure 4), and another one thereof is close to the second edge (Seen n Figure 4); and the second functional pin (Figure 4, Elements Fault. Paragraph 25) is electrically connected to the first functional pin (Figure 4, Elements Ena. Paragraph 25) through a first connection line (Seen in Figure 4).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. with the teachings of the addressing method of Yang et al. The motivation to modify the teachings of Xu et al. with the teaching of Yang et al. is to provide an addressing method for a plurality of chips, as taught by Yang et al. (Paragraph 12).
Regarding Claim 6, Xu et al. teach the light-emitting substrate according to claim 1 (See Above). Xu et al. is silent with regards to wherein the driver chip further includes an address pin and a relay pin; and among driver chips connected to the plurality of device groups, a relay pin of a former-stage driver chip is electrically connected to an address pin of a latter-stage driver chip through a second external connection line.
Yang et al. teach wherein the driver chip (Figure 4, Elements 120. Paragraph 25) further includes an address pin (Figure 4, Elements Ena. Paragraph 25) and a relay pin (Figure 4, Elements Fault. Paragraph 25); and among driver chips (Figure 4, Elements 120. Paragraph 25) connected to the plurality of device groups, a relay pin (Figure 4, Elements Fault. Paragraph 25) of a former-stage driver chip (Figure 4, Elements 120. Paragraph 25) is electrically connected to an address pin (Figure 4, Elements Ena. Paragraph 25) of a latter-stage driver chip (Figure 4, Elements 120. Paragraph 25) through a second external connection line (Seen in Figure 4).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. with the teachings of the addressing method of Yang et al. The motivation to modify the teachings of Xu et al. with the teaching of Yang et al. is to provide an addressing method for a plurality of chips, as taught by Yang et al. (Paragraph 12).
Regarding Claim 7, Xu et al. in view of Yang et al. teach the light-emitting substrate according to claim 6 (See Above). Xu et al. is silent with regards to further comprising a conductive layer, wherein the conductive layer includes an address signal line electrically connected to an address pin of a first-stage driver chip.
Yang et al. teach further comprising a conductive layer (Element not labeled, but is the layer containing the wiring. Paragraphs 25 – 26), wherein the conductive layer (Element not labeled, but is the layer containing the wiring. Paragraphs 25 – 26) includes an address signal line (Figure 4, Element not labeled, but is the line leading into Ena of chip 1. Paragraph 25) electrically connected to an address pin (Figure 4, Elements Ena. Paragraph 25) of a first-stage driver chip (Figure 4, Element Chip 1 (120). Paragraph 25).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. with the teachings of the addressing method of Yang et al. The motivation to modify the teachings of Xu et al. with the teaching of Yang et al. is to provide an addressing method for a plurality of chips, as taught by Yang et al. (Paragraph 12).
Regarding Claim 9, Xu et al. in view of Yang et al. teach the light-emitting substrate according to claim 6 (See Above). Xu et al. teach wherein first functional pins (Figures 1 - 6, Element Vtest. Paragraph 33) of the driver chips (Figures 1 - 6, Element IC. Paragraph 28) connected to the plurality of device groups (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89) are electrically connected (Seen in Figure 6).
Claims 11 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (U.S. PG Pub 2017/0059897) in view of Yang et al. (U.S. PG Pub 2011/0018888) in view of Ghaderi et al. (U.S. Patent No. 9,472,131).
Regarding Claim 11, Xu et al. in view of Yang et al. teach the light-emitting substrate according to claim 6 (See Above). Xu et al. is silent with regards to wherein the driver chip further includes at least one ground pin, and the at least one ground pin is capable of receiving a ground signal.
Ghaderi et al. teach wherein the driver chip (Figure 2, Element 5. Column 4, Lines 39 – 62) further includes at least one ground pin (Figure 2, Element 3. Column 4, Lines 39 – 62), and the at least one ground pin (Figure 2, Element 3. Column 4, Lines 39 – 62) is capable of receiving a ground signal (Figure 2, Element ground. Column 4, Lines 39 – 62).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. and the teachings of the addressing method of Yang et al. with the grounding pin of Ghaderi et al. The motivation to modify the teachings of Xu et al. and Yang et al. with the teachings of Ghaderi et al. is to provide a power return node, as taught by Ghaderi et al. (Column 4, Lines 39 – 62).
Regarding Claim 12, Xu et al. in view of Yang et al. in view of Ghaderi et al. teach the light-emitting substrate according to claim 11 (See Above). Xu et al. is silent with regards to further comprising a conductive layer, wherein the conductive layer includes a ground line electrically connected to the at least one ground pin, and the ground line is configured to provide the ground signal for the at least one ground pin.
Ghaderi et al. teach further comprising a conductive layer (Seen in Figure 1), wherein the conductive layer (Seen in Figure 1) includes a ground line (Figure 2, Element ground. Column 4, Lines 39 – 62) electrically connected to the at least one ground pin (Figure 2, Element 3. Column 4, Lines 39 – 62), and the ground line (Figure 2, Element ground. Column 4, Lines 39 – 62) is configured to provide the ground signal for the at least one ground pin (Figure 2, Element 3. Column 4, Lines 39 – 62).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the testing of driver chips of Xu et al. and the teachings of the addressing method of Yang et al. with the grounding pin of Ghaderi et al. The motivation to modify the teachings of Xu et al. and Yang et al. with the teachings of Ghaderi et al. is to provide a power return node, as taught by Ghaderi et al. (Column 4, Lines 39 – 62).
Regarding Claim 13, Xu et al. in view of Yang et al. in view of Ghaderi et al. teach the light-emitting substrate according to claim 11 (See Above). Xu et al. teach wherein the driver chip (Figures 1 - 6, Element IC. Paragraph 28) further includes a first power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58), and the first power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58) is capable of receiving a power supply signal (Figures 4 - 6, Element VDD. Paragraphs 57 - 58).
Regarding Claim 14, Xu et al. in view of Yang et al. in view of Ghaderi et al. teach the light-emitting substrate according to claim 13 (See Above). Xu et al. teach wherein the driver chip (Figures 1 - 6, Element IC. Paragraph 28) further includes a second power supply pin electrically connected to the first power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58); and
among the driver chips (Figures 1 - 6, Element IC. Paragraph 28) connected to the plurality of device groups (Figures 1 - 6, Element not shown, but is the portion of the display device that is driven by the control circuit board. Paragraphs 3 and 89), a second power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58) of the former-stage driver chip (Figures 1 - 6, Element IC. Paragraph 28) is electrically connected to a first power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58) of the latter-stage driver chip (Figures 1 - 6, Element IC. Paragraph 28) through a third external connection line (Figure 6. The examiner notes that both IC chips are receiving the same signal from the same source.).
Regarding Claim 15, Xu et al. in view of Yang et al. in view of Ghaderi et al. teach the light-emitting substrate according to claim 13 (See Above). Xu et al. teach further comprising a conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89), wherein the conductive layer (Figures 1 - 6, Element not shown, but is line connecting the connecting the testing circuit and the display panel. Paragraphs 3 and 89) includes a first voltage line electrically connected to a first power supply pin (Figures 4 - 6, Element VDD. Paragraphs 57 - 58) of a first-stage driver chip (Figures 1 - 6, Element IC. Paragraph 28); and the first voltage line is configured to provide a power supply signal for each driver chip (Figures 1 - 6, Element IC. Paragraph 28).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach at least “wherein the address pin is capable of receiving driving data; the driving data includes address verification information and a plurality of pieces of driving information corresponding to the driver chips; and the driver chip is configured to: obtain, according to the address verification information, a piece of driving information corresponding to the driver chip; output, according to the piece of driving information, at least one driving current to the at least one light-emitting unit connected to the driver chip; update the address verification information and output driving data including the updated address verification information from the relay pin” of Claim 8 in combination with the limitations of Claims 6 and 1 from which Claims 8 depends.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach at least “the first functional pin is further capable of receiving driving data, and the driving data includes a plurality of pieces of address verification information and a plurality of pieces of driving information corresponding to the plurality of pieces of address verification information; and the driver chip is configured to: configure address information of the driver chip according to the address signal received by the address pin and generate a relay signal; output the relay signal from the relay pin; and when a piece of address verification information in the plurality of pieces of address verification information matches the address information of the driver chip, receive a corresponding piece of driving information according to the piece of address verification information, and output at least one driving current to the at least one light-emitting unit connected to the driver chip according to the received driving information, wherein a relay signal output by the relay pin of the former-stage driver chip serves as an address signal of the latter-stage driver chip” of Claim 10 in combination with the limitations of Claims 9, 6, and 1 from which Claims 10 depends.
Claims 16 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach at least “wherein the driver chip further includes a second functional pin electrically connected to the first functional pin; and among the driver chips connected to the plurality of device groups, a second functional pin of the former-stage driver chip is electrically connected to a first functional pin of the latter-stage driver chip; the driver chip has a first edge and a second edge that are parallel to each other, and a third edge located between a first end of the first edge and a first end of the second edge; one of the first functional pin and the second functional pin is close to the first edge, and another one thereof is close to the second edge; and one of the address pin and the relay pin is close to the first edge, and another one thereof is close to the second edge; and the address pin and the relay pin are both closer to the third edge than the first functional pin and the second functional pin” of Claim 16 in combination with the limitations of Claims 13 – 14, 11, 6, and 1 from which Claims 16 depends. Claims 17 – 18 inherit this objection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al. (U.S. PG Pub 2012/0105085) discloses a test circuit for a display driver similar to the instant application.
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/A.B.S/Examiner, Art Unit 2625 /WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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