DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 10-2024-0092841, filed on 15th, Jul. 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SUN et al. (US Patent/PGPub. No. 20240257732).
Regarding Claim 1,
SUN et al. teach
a pixel ([0123], FIG. 11, i.e. pixel driving circuit), comprising:
a light emitting diode ([0125], FIG. 11, i.e. light emitting unit OLED);
a driving transistor ([0119], FIG. 11, i.e. driving transistor T3) connected to a high potential driving voltage line ([0123], FIG. 11, i.e. second power terminal VDD (indirectly via T5 as shown by the figure)) and a first node ([0123], FIG. 11, i.e. third node N3), the driving transistor having a gate electrode ([0117], FIG. 11, i.e. gate of the driving transistor T3) connected to a second node ([0117], FIG. 11, i.e. gate of the driving transistor T3 is coupled to a first node N1);
a switching transistor ([0126], FIG. 11, i.e. fourth transistor T4) connected to a data line ([0122], FIG. 11, i.e. second electrode of the fourth transistor T4 is coupled to the data signal terminal Vdata) and the second node (FIG. 11, i.e. indirectly connected to N1 via T3 as shown by the figure), the switching transistor having a gate electrode configured to receive a first scan signal ([0122], FIG. 11, i.e. gate of the fourth transistor T4 is coupled to the first gate driving signal terminal G1);
an initialization transistor ([0126], FIG. 11, i.e. first transistor T1) connected to a reference voltage line ([0126], FIG. 11, i.e. first initial signal terminal Vinit1) and the second node ([0126], FIG. 11, i.e. second electrode the first transistor T1 is coupled to the first node N1), the initialization transistor having a gate electrode ([0126], FIG. 11, i.e. gate of the first transistor T1) configured to receive a second scan signal ([0126], FIG. 11, i.e. gate of the first transistor T1 is coupled to the first reset signal terminal Re1);
a first capacitor ([0126], FIG. 11, i.e. third capacitor C3) connected to the first node (FIG. 11, i.e. indirectly connected to N3 via T5 and T3 as shown by the figure) and the second node ([0126], FIG. 11, i.e. third capacitor C3 coupled between the first node N1);
a second capacitor ([0126], FIG. 11, i.e. first capacitor C1) having one electrode (FIG. 11, i.e. right electrode of C1 as shown by the figure) connected to the first node (FIG. 11, i.e. right electrode of C1 indirectly connected to N3 via T3 as shown by the figure);
a third capacitor ([0126], FIG. 11, i.e. second capacitor C2) connected to the first node (FIG. 11, i.e. indirectly connected to N3 via T2 as shown by the figure) and the reference voltage line (FIG. 11, i.e. indirectly connected to Vinit1 via T1 as shown by the figure); and
a compensation transistor ([0126], FIG. 11, i.e. second transistor T2; [0122], FIG. 11, i.e. compensation circuit 8 may include a N-type second transistor T2) connected to the third capacitor (FIG. 11, i.e. gate of T2 connected to C2 as shown by the figure) and the reference voltage line (FIG. 11, i.e. right electrode of T2 connected to Vinit1 via T1 as shown by the figure), the compensation transistor having a gate electrode ([0122], FIG. 11, i.e. gate of the second transistor T2) configured to receive a fourth scan signal ([0122], FIG. 11, i.e. gate of the second transistor T2 is coupled to the second gate driving signal terminal G2).
Regarding Claim 10,
SUN et al. teach
the pixel of claim 1, wherein another electrode of the second capacitor (FIG. 11, i.e. left electrode of C1 as shown by the figure) is connected to the high potential driving voltage line (FIG. 11, i.e. left electrode of C1 indirectly connected to VDD via T4 and T5 as shown by the figure) or a capacitor driving voltage line (i.e. alternative limitation(s) omitted).
Allowable Subject Matter
4. Claim(s) 11-19 is/are allowed.
5. Claim(s) 2-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for allowance:
SUN et al. (US Patent/PGPub. No. 20240257732) teach a pixel driving circuit includes a driving circuit, a first reset circuit, and a second reset circuit. The driving circuit is coupled to a first node and a second node, and is configured to output a driving current according to a voltage difference between the first node and the second node. The first reset circuit is coupled to the first node, a first initial signal terminal and a first reset signal terminal, and is configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the first reset signal terminal. The second reset circuit is coupled to the second node and a first power terminal, and is configured to transmit a signal of the first power supply terminal to the second node in response to a control signal.
HWANG et al. (US PGPUB./Pat. No. 20230154372) teach a display device includes PAM data lines receiving PAM and PWM data voltages, and sub-pixels connected to the PAM and PWM data lines. A sub-pixel includes a light emitting element, a first pixel driver to supply a control current according to one of the PAM data voltages to a node, a second pixel driver to generate a driving current according to one of the PWM data voltages, and a third pixel driver to adjust a period during which the driving current is supplied to the light emitting element according to a voltage of the node. A peak current value of the driving current when the sub-pixel emits a light corresponding to a low gray level region is smaller than a peak current value of the driving current when the sub-pixel emits a light corresponding to a high gray level region higher than the low gray level region.
The subject matter of the independent claims could either not be found or was not suggested in the prior art of record. The subject matter neither found nor obvious combination of references that may produce inoperativeness or teaching away from one another was a display device including
“…the third capacitor stores a voltage corresponding to a threshold voltage of the driving transistor while the compensation transistor is turned on during a non-emission period of the light emitting diode, and the third capacitor is floated while the compensation transistor is turned off during an emission period of the light emitting diode.” (Claim 2),
“…the fourth scan signal is applied in a turn-on level during a non-emission period of the light emitting diode and is applied in a turn-off level during an emission period of the light emitting diode.” (Claim 3),
“…a first light emitting transistor connected to the high potential driving voltage line and the driving transistor, the first light emitting transistor having a gate electrode configured to receive a first light emission signal;
a second light emitting transistor connected to the first node and the light emitting diode, the second light emitting transistor having a gate electrode configured to receive a second light emission signal; and
an anode initialization transistor connected to the light emitting diode and a bias voltage line, the anode initialization transistor having a gate electrode configured to receive a third scan signal.” (Claim 4),
“…an area of the second capacitor and an area of the third capacitor are smaller than an area of the first capacitor.” (Claim 7),
“…a first insulation layer on the substrate;
a first storage electrode on the first insulation layer;
a second insulation layer on the first storage electrode;
a second storage electrode to a fourth storage electrode on the second insulation layer and having at least one region thereof, respectively, overlapping the first storage electrode;
a third insulation layer on the second storage electrode to the fourth storage electrode;
a fifth storage electrode and a sixth storage electrode on the third insulation layer and overlapping the second storage electrode and the fourth storage electrode, respectively;
a fourth insulation layer on the fifth storage electrode and the sixth storage electrode;
wherein the driving transistor is on the fourth insulation layer and the light emitting diode is on the driving transistor.” (Claim 8),
“…a gate driver configured to apply a first scan signal to a fourth scan signal and a first light emission signal and a second light emission signal to the pixels...
…a switching transistor configured to apply the data voltage to the second node in response to the first scan signal;
an initialization transistor configured to apply a reference voltage to the second node in response to the second scan signal;
an anode initialization transistor configured to apply a bias voltage to the light emitting diode in response to the third scan signal;
a first light emitting transistor connecting the high potential driving voltage line and the driving transistor to each other in response to the first light emission signal;
a second light emitting transistor connecting the first node and the light emitting diode to each other in response to the second light emission signal…” (Claim 11),
“…in a refresh period in one frame,
an initializing step during which the gate driver applies a second scan signal, a third scan signal, a fourth scan signal, and a second light emission signal in a turn-on level;
a sampling step during which the gate driver converts the second light emission signal into a turn-off level and applies a first light emission signal in the turn-on level;
a programming step during which the gate driver converts the second scan signal and the first light emission signal into the turn-off level, and applies a first scan signal in the turn-on level, and the data driver applies the data voltage;
a boosting step during which the gate driver converts the first scan signal, the third scan signal, and the fourth scan signal into the turn-off level, and converts the first light emission signal and the second light emission signal into the turn-on level; and
a light emitting step during which the pixel emits light at a luminance corresponding to the data voltage.” (Claim 16),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571)270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VINH T LAM/Primary Examiner, Art Unit 2628