DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Election
Applicant’s election with traverse, in the reply filed September 14, 2026, of the invention of Group I is acknowledged. The elected invention of Group I, encompassing claims 1–6, will be examined on the merits. Applicant’s reply, however, does not distinctly and specifically point out the supposed errors in the restriction requirement. Accordingly, the election is treated as an election without traverse. The restriction requirement is therefore deemed proper and is made FINAL.
Claims 7–12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to the non-elected invention. Accordingly, a complete reply to this Office action must include cancellation of claims 7–12, which are directed to the non-elected Group.
Specification
The disclosure is objected to because of the following informalities: paragraph [0001], line 2, now U.S. Patent No. 12,401,293 issued on 08/26/2025,-- should be inserted after “filed December 8, 2022,”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Campbell et al. (US 8,675,376 B2, hereinafter “Campbell”) in view of Hohmann et al. (US 2021/0408941, hereinafter “Hohmann”).
With regard to Claim 1, Campbell teaches a system including an inverter having power electronic switches and local power-layer circuitry configured to generate gate-drive signals for controlling the conductive states of the power electronic switches (see Campbell, Figs. 1–9). Regarding “a power module for an inverter for an electric vehicle,” Campbell teaches inverter circuitry 36 including power electronic switches 54, 76, including high-side switch 78 and low-side switch 80, coupled across DC bus 30, wherein coordinated switching of the switches between conducting and non-conducting states generates a controlled output waveform (Campbell, Figs. 1–5; see particularly Fig. 4). Campbell further teaches that a number of the power switches may be provided on a common support and coupled together to provide the desired power capacity. Campbell does not expressly disclose that the inverter is specifically an inverter for an electric vehicle. Hohmann teaches a power module for operating an electric vehicle drive, wherein the power module is preferably used in a DC/AC inverter for supplying an electric machine, such as an electric motor, from DC power supplied by a power source such as a battery (Hohmann, Fig. 1 and paragraphs [0025] – [0027]). Hohmann further teaches that the power module contains semiconductor-based high-side and low-side topological switches controlled by control electronics. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the inverter power circuitry and synchronized gate-control architecture taught by Campbell in the electric-vehicle inverter power module taught by Hohmann. Hohmann expressly teaches the applicability of such semiconductor switching power modules to electric-vehicle DC/AC inverters, while Campbell teaches synchronized local gate-drive generation for accurately controlling semiconductor switches of an inverter. The combination would have predictably provided synchronized switching control of the semiconductor switches of an electric-vehicle inverter.
Regarding “the power module comprising: a power switch including a drain terminal, a source terminal, and a gate terminal,”. Campbell teaches semiconductor power switches 54, 76, including high-side power switch 78 and low-side power switch 80, for selectively converting DC-bus power to a controlled inverter output (Campbell, Fig. 1). Campbell does not expressly teach that the power switch comprises terminals specifically denominated drain, source, and gate terminals. Hohmann expressly teaches semiconductor components 112a-c and 113a-c forming high-side topological switch 112 and low-side topological switch 113, wherein each semiconductor component may be a MOSFET and comprises a gate connection G, drain connection D, and source connection S (Hohmann, Fig. 2 and paragraphs [0028]). It would have been obvious to one of ordinary skill in the art to implement Campbell’s inverter power switches using the MOSFET power switches taught by Hohmann because Hohmann expressly teaches MOSFETs as suitable power semiconductor components for an electric-vehicle inverter. Such implementation would have amounted to the use of a known power semiconductor switching device for its known function of selectively conducting inverter current in response to a gate-control signal, with predictable results.
Regarding “a gate driver configured to provide a signal to the gate terminal to control an operation of the power switch,” Campbell teaches power-layer interface circuitry including FPGA 70 and power circuit interface 72 configured to generate drive signals for power circuitry 74 and power switches 76 (Campbell, Figs. 3–4). Campbell further teaches generating timing signals for the high-side and low-side switches and generating pulse-width-modulated signals for driving the solid-state switches (Campbell, Figs. 6–8). Hohmann additionally expressly teaches control electronics comprising a controller component for generating a control signal and a driver for controlling the power switch based on the control signal. Hohmann further teaches control electronics 116 located between voltage source 117 and gate connection G of semiconductor component 112a and configured to set the gate current supplied to the gate connection (Hohmann, Figs. 2–3). Thus, Campbell in view of Hohmann teaches or suggests a gate driver configured to provide a signal to the gate terminal to control operation of the power switch.
Regarding “a point-of-use phase controller,” Campbell teaches local power-layer interface circuitry associated with each inverter, including FPGA 70 provided at the power layer and configured to locally compute or recompute timing information used for controlling the conductive states of the inverter power switches (Campbell, Figs. 3 and 5–8). Campbell expressly distinguishes the processing performed at the power layer from processing performed at the central control circuitry and teaches that the gate-drive timing computations are performed locally at the power layer. Thus, Campbell’s FPGA 70 and associated power-layer interface circuitry correspond to the claimed point-of-use phase controller because the circuitry is locally disposed at the inverter power layer and performs timing/phase processing used to control the inverter switches.
Regarding the point-of-use phase controller being configured to “align a clock reference signal of the point-of-use phase controller with a clock reference signal of a high voltage phase controller,” Campbell teaches that each local power-layer FPGA operates according to its own oscillator and clock and generates or recomputes gate-drive timing in synchronization with timing originating from the control circuitry (Campbell, Figs. 5–7). More particularly, Campbell teaches that synchronization data is transmitted from control circuitry FPGA 58 to the local power-layer circuitry. The transmitted synchronization data allows clock-data recovery at the power layer, and a carrier waveform signal transmitted by the control circuitry facilitates the clock recovery. Campbell further expressly teaches that a phase comparison is performed by each power layer, which, in conjunction with the recovered clock data, provides synchronization of the gate-drive signals (Campbell, Figs. 5–7). Campbell therefore teaches a local controller having its own local clock reference and synchronizing the locally generated timing with timing/clock information originating from another controller. Campbell additionally teaches correcting differences between the local oscillator and the reference timing. Specifically, when the power-layer circuitry detects drift of its oscillator relative to the received clock information, the power-layer circuitry corrects the drift by adding or subtracting a clock cycle, thereby at least partially correcting accumulated timing error (Campbell, Figs. 13–14 and Column 13, line 25 - Column 15, line 28). Accordingly, Campbell teaches not merely using two clocks, but actively aligning/synchronizing the local clock timing with externally supplied reference timing.
Furthermore, Campbell’s Fig. 9 provides an alternative embodiment even more directly corresponding to the claimed limitation. Campbell teaches that an additional optical fiber 144 may transmit a clock signal from the control circuitry directly to each power-layer interface. Campbell explains that, using the transmitted clock signal, recomputation of the timing signals at the local power-layer interface is performed in synchronicity based upon the transmitted clock signal (Campbell, Fig. 9 and Column 9, line 46 - Column 10, line 2). Thus, Campbell teaches or suggests a point-of-use controller configured to align its local clock/timing reference with a clock reference originating from another controller. Although Campbell does not refer to the upstream controller using the particular nomenclature “high voltage phase controller,” Campbell’s control circuitry provides the reference clock/timing information to which the local power-layer timing is synchronized. The difference in nomenclature does not patentably distinguish the claimed functional relationship where the prior art circuitry performs the claimed clock-reference synchronization function.
Regarding “and control the gate driver based on the clock reference signal of the point-of-use phase controller,” Campbell expressly teaches using the locally synchronized timing to generate the inverter gate-drive signals. Specifically, Campbell teaches that control circuitry sends signals to the power-layer circuitry permitting the power-layer circuitry to compute or recompute timing for changing the conductive state of the solid-state switches. The computation is based on reconstruction of a carrier waveform using a recovered clock step and a triangle waveform accumulator (Campbell, Figs. 6–7). Campbell further teaches that after the clock timing is recovered at the inverter, timing signals are reconstructed in the power-layer interface circuitry and pulse-width-modulated signals are generated for driving the solid-state switches (Campbell, Fig. 8). Accordingly, the clock/timing reference locally recovered and synchronized by Campbell’s power-layer circuitry is used to determine the timing of the gate-drive signals controlling the semiconductor switches. Campbell therefore teaches or suggests controlling the gate driver based on the clock reference signal of the point-of-use controller.
In view of the foregoing, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Campbell’s inverter and synchronized power-layer gate-control architecture to employ the electric-vehicle power-module configuration and MOSFET power switches taught by Hohmann. One would have been motivated to make the modification because Hohmann teaches MOSFET-based power modules specifically adapted for DC/AC inverters of electric-vehicle drives, while Campbell teaches synchronized local generation of gate-drive timing for controlling semiconductor inverter switches. The combination would have predictably resulted in an electric-vehicle inverter power module having MOSFET power switches controlled by gate-drive circuitry whose switching timing is based upon locally synchronized clock/timing information. Therefore, Campbell in view of Hohmann teaches or suggests all of the limitations of claim 1.
With regard to Claim 6, Claim 1 is unpatentable over Campbell in view of Hohmann for the reasons set forth above. Claim 6 further recites that “the clock reference signal of the high voltage phase controller has a frequency from approximately 100 Hz to approximately 10 kHz.” Campbell in view of Hohmann teaches the claimed system, including a clock reference signal used for synchronization of the local power-layer control circuitry, but does not expressly disclose that the clock reference signal has a frequency within the recited range of approximately 100 Hz to approximately 10 kHz. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select or adjust the frequency of the clock reference signal, including selecting a frequency within the recited range, as a matter of routine optimization based on the timing, synchronization, switching, and communication requirements of the particular inverter application. The frequency of a clock reference signal is a result-effective variable because variation of the reference frequency predictably affects the timing and synchronization characteristics of the associated control circuitry. Accordingly, one of ordinary skill in the art would have had reason to select an appropriate reference-clock frequency through routine experimentation to obtain the desired synchronization and operating characteristics of the inverter control system. Where the general conditions of a claim are disclosed in the prior art, discovering an optimum or workable range by routine experimentation is ordinarily not patentable. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Moreover, the discovery of an optimum value of a result-effective variable is ordinarily within the skill of the art. See In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980). Therefore, it would have been obvious to one of ordinary skill in the art to select the frequency of the clock reference signal taught or suggested by Campbell in view of Hohmann to be within the recited range of approximately 100 Hz to approximately 10 kHz in order to provide a suitable clock-reference frequency for the particular inverter control and synchronization requirements. Accordingly, claim 6 is unpatentable over Campbell in view of Hohmann.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Campbell et al. in view of Hohmann et al., as applied to claim 1 above, and further in view of DeCruyenaere et al. (US 2008/0298533, hereinafter “DeCruyenaere”).
With regard to Claim 2, Campbell in view of Hohmann teaches the system of claim 1 for the reasons set forth above, including a local/point-of-use controller having local clock timing synchronized with clock/timing information originating from another controller. Regarding “wherein the point-of-use phase controller is configured to align the clock reference signal of the point-of-use phase controller with the clock reference signal of the high voltage phase controller by counting a number of system clock pulses in one or more periods of the clock reference signal of the high voltage phase controller and comparing a counted number to an expected value,” Campbell teaches synchronization of a local oscillator/clock of the power-layer interface circuitry with clock information supplied by the control circuitry, but does not expressly disclose performing the synchronization by counting local/system-clock pulses during one or more periods of the reference signal and comparing the resulting count to an expected value. DeCruyenaere teaches a system for synchronizing a local clock signal 165 generated by local oscillator 170 with a reference clock signal 120 (Fig. 2; see also the description associated with Figs. 2–5). DeCruyenaere teaches reference counter block 110, feedback counter block 150, controller block 160, local oscillator 170, and adder 185. More particularly, reference counter block 110 receives reference clock signal 120 and generates hit signal 140 at predetermined intervals of the reference clock. Feedback counter block 150 receives the local clock signal 165 generated by local oscillator 170 and counts the number of pulses of the local clock between successive hit signals. The resulting feedback count 180 therefore represents the number of local/system-clock pulses occurring during an interval defined by the reference clock signal (DeCruyenaere, Fig. 2 and see also the description associated with Fig. 2). DeCruyenaere further teaches that feedback count signal 180 is supplied to adder 185, which compares the feedback count with predetermined feedback value (Nf 187) by subtracting the predetermined feedback value from the counted value, thereby generating count error signal 190 (DeCruyenaere, Fig. 2). Thus, the predetermined feedback value Nf constitutes an expected value against which the actual number of counted local-clock pulses is compared. DeCruyenaere further explains that the nominal period of the reference clock is Tr, the nominal period of the local clock is Tx, and the predetermined reference and feedback values Nr and Nf are selected according to the relationship Nf/Nr = Tr/Tx. Thus, the expected local-clock count is established based upon the reference-clock period. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ DeCruyenaere’s counter-based frequency-alignment technique in Campbell’s local power-layer controller in order to synchronize Campbell’s local oscillator with the clock reference supplied by the control circuitry. DeCruyenaere expressly teaches that such counting and comparison provides a digital frequency-locked-loop technique for synchronizing a local oscillator to a reference clock. The modification would have provided the predictable benefit of detecting clock-frequency deviation and correcting local-oscillator drift using straightforward digital counting circuitry. Accordingly, Campbell in view of Hohmann and DeCruyenaere teaches or suggests the limitations of claim 2.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Campbell et al. in view of Hohmann et al. and DeCruyenaere et al., as applied to claim 2 above.
With regard to Claim 3, the combination teaches the system of claim 2 for the reasons set forth above. Regarding “wherein the point-of-use phase controller is further configured to increase or decrease a period of an internal oscillator of the point-of-use phase controller to align the counted number to the expected value,”. DeCruyenaere expressly teaches that count error signal 190, representing the difference between feedback count 180 and predetermined feedback value (Nf 187), is supplied to controller block 160. Controller block 160 generates frequency-adjust signal 195, which adjusts local oscillator 170 (Figs. 2 and 5). DeCruyenaere teaches that when the local oscillator frequency is lower than the reference-clock frequency, the frequency-adjust signal causes the local oscillator frequency to increase; conversely, when the local oscillator frequency is higher than the reference-clock frequency, the frequency-adjust signal causes the local oscillator frequency to decrease (see Fig. 5 and associated description). Because frequency and period are reciprocally related, increasing oscillator frequency decreases oscillator period, while decreasing oscillator frequency increases oscillator period. Accordingly, DeCruyenaere’s increase/decrease of the local oscillator frequency necessarily corresponds to decreasing/increasing the oscillator period, respectively. The adjustment is based specifically upon the difference between the actual counted number of local-clock pulses and predetermined feedback value Nf. Thus, DeCruyenaere teaches adjusting the period/frequency of the internal oscillator so as to bring the counted value toward the expected value. It would have been obvious to employ this known oscillator-adjustment technique in the modified Campbell system for the same reason discussed with respect to claim 2, namely, to correct detected frequency error and synchronize the local oscillator to the reference clock. Accordingly, Campbell in view of Hohmann and DeCruyenaere teaches or suggests the limitations of claim 3.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Campbell et al. in view of Hohmann et al. and DeCruyenaere et al., as applied to claim 3 above.
With regard to Claim 4, the combination teaches the system of claim 3 for the reasons set forth above. Regarding “wherein the point-of-use phase controller is further configured to iteratively perform an alignment of an oscillator of the point-of-use phase controller with the clock reference signal of the high voltage phase controller,” DeCruyenaere teaches that the synchronization process is repeatedly performed. Specifically, reference counter block (110 in Figs. 2 and 6) repeatedly produces hit signal 140 when the predetermined number of reference-clock pulses has occurred. Upon each hit signal, feedback counter block 150 provides the count of local oscillator pulses occurring during the corresponding reference interval, and controller block 160 updates frequency-adjust signal 195 based upon count error signal (190 in Figs. 2–5). DeCruyenaere further teaches that controller circuit (400 of Fig. 5) updates the frequency-adjust signal each time a hit signal is generated by accumulating the count-error information. The resulting frequency-adjust signal represents cumulative tracking of the difference between the local oscillator frequency and reference-clock frequency. Thus, DeCruyenaere teaches an iterative closed-loop alignment process, rather than merely a single calibration operation. Regarding “so that successive counts of the number of system clock pulses brings the oscillator of the point-of-use phase controller into alignment with the clock reference signal of the high voltage phase controller,” DeCruyenaere teaches that each successive feedback count is compared with predetermined feedback value Nf and that the resulting error is used to update frequency-adjust signal 195. The frequency of local oscillator 170 is consequently increased or decreased based upon the successive count errors until the local oscillator tracks the reference-clock frequency. DeCruyenaere further teaches that frequency synchronization preferably entails tracking the reference frequency and adjusting the local-clock frequency to account for changes in the reference frequency. It therefore would have been obvious to configure the modified Campbell local controller to perform DeCruyenaere’s synchronization procedure iteratively, because repeated measurement and correction permits the local oscillator to converge toward and thereafter track the reference clock despite oscillator drift or changing conditions.
Accordingly, Campbell in view of Hohmann and DeCruyenaere teaches or suggests the limitations of claim 4.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 September 25, 2026
