Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 1 recites “a CXL.mem module including a prefetch module configured to prefetch…”
Claim 3 recites “a CXL.io module… configured to store…”
Dependent claims 6-8 also recite the 112(f) limitations identified above for claims 1 and/or 3.
Claim 11 recites “a CXL.io module configured to set…” and “a CXL.mem module configured to: receive… decode… prefetch…”
Dependent claims 12-15 also recite the 112(f) limitations identified above for claims 11.
Claim 16 recites “a CXL.mem module configured to: receive… prefetch… and store…”
Dependent claims 17-19 also recite the 112(f) limitations identified above for claims 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
For example, the instant application discusses that the prefetch module, which is claimed as part of the CXL.mem module, includes a prefetch controller and a prefetch memory [0073].
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon et al. (US 2025/0378031 A1) hereinafter Kwon et al.
Regarding claim 1, Kwon et al. teaches a Compute Express Link (CXL) device (memory expanding device 200) connected to a host device and a memory device (is connected to host device 100 and memory device 220, note that these components are all connected via compute express link (CXL) interface Paragraph [0043]), the CXL device comprising:
a CXL host interface receiving a prefetch request including a prefetch indicator from the host device (host device includes a prefetch support circuit which generates prefetch information required to prefetch data and transmit the prefetch information to the memory expanding device through a root complex Paragraph [0045]);
a CXL.mem module including a prefetch module configured to prefetch first data corresponding to the prefetch indicator from the memory device, and store the prefetched first data (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]); and
a memory controller configured to access the memory device (memory controller 210 may control the overall operation of the memory expanding device and includes the prefetch decision circuit Paragraph [0070]), wherein the CXL device is configured to read the first data from the prefetch module and output the first data to the host device based on the first data corresponding to requested data associated with an access request received from the host device (prefetch decision circuit may prefetch prefetch data into the prefetch buffer of the host device at a prefetch time Paragraph [0083]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2025/0378031 A1) hereinafter Kwon et al. in view of Bert et al. (US 2025/0013570 A1) hereinafter Bert et al.
Regarding claim 2, Kwon et al. teaches all of the features with respect to claim 1 as outlined above.
Kwon et al. further teaches a prefetch memory configured to store at least one first data in at least one slot mapped to the prefetch indicator (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]); and a prefetch controller configured to: store the prefetch indicator, and perform data access to a slot mapped to the prefetch indicator in the prefetch memory based on an address of the requested data being matched with the prefetch indicator (the prefetch decision circuit stores a program counter and memory address, where the memory address is an address in which data required by the host device is stored within the memory expanding device Paragraph [0056], and when a cache hit occurs in the cache controller, the prefetch support circuit transmits the cache hit info and prefetch info to the memory expanding device to be retrieved through a root complex and stored inside the prefetch buffer Paragraph [0057], [0066]).
Kwon et al. does not appear to explicitly teach, however, Bert et al. teaches to store the prefetch indicator in a lookup table (the memory sub-system 110 manages an address map 155 identifying the correlations between pages 177 of the cache memory and pages 167 of storage memory in the loadable portion Paragraph [0114], where the storage memory page ID 165 identifies a corresponding memory address which identifies a storage location of the memory cells Paragraphs [0118]-[0121]).
Kwon et al. and Bert et al. both teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of Kwon et al. and Bert et al., hereinafter KB, before the effective filing date of the invention, to modify the teachings of Kwon et al. by including a CXL.io module comprising a plurality of slots configured to store the prefetch indicators, as taught by Kwon et al.
One of ordinary skill in the art would have been motivated to include a CXL.io module comprising a plurality of slots configured to store the prefetch indicators to utilize the information as part of an address map to determine whether certain pages of a storage are cached according to the map.
Regarding claim 3, Kwon et al. teaches all of the features with respect to claim 1 as outlined above.
Kwon et al. does not appear to explicitly teach, however, Bert et al. teaches further comprising a CXL.io module comprising a plurality of slots (a plurality of entries of pages of the address map 155), each of the plurality of slots configured to store at least one prefetch indicators (the memory sub-system 110 manages an address map 155 identifying the correlations between pages 177 of the cache memory and pages 167 of storage memory in the loadable portion Paragraph [0114], where the storage memory page ID 165 identifies a corresponding memory address which identifies a storage location of the memory cells Paragraphs [0118]-[0121]).
Kwon et al. and Bert et al. both teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of Kwon et al. and Bert et al., hereinafter KB, before the effective filing date of the invention, to modify the teachings of Kwon et al. by including a CXL.io module comprising a plurality of slots configured to store the prefetch indicators, as taught by Kwon et al.
One of ordinary skill in the art would have been motivated to include a CXL.io module comprising a plurality of slots configured to store the prefetch indicators to utilize the information as part of an address map to identify correlations between the prefetched data and pages of storage memory.
Regarding claim 4, KB teaches all of the features with respect to claim 3 as outlined above.
Bert et al. teaches wherein the prefetch indicator comprises an address information about a position in the memory device in which the first data is stored (storage memory page ID identifies a page of the memory space Paragraphs [0149]-[0150]), and at least one of prefetch control information and prefetch status information (page status 171 of address map, see Fig. 4).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over KB in further view of Tanaka et al. (US 2010/0318707 A1) hereinafter Tanaka et al.
Regarding claim 5, KB teaches all of the features with respect to claim 4 as outlined above.
KB does not appear to explicitly teach, however, Tanaka et al. teaches wherein the at least one of the prefetch control information and the prefetch status information indicates whether the prefetch request is received from the host device for each slot from among the plurality of slots, and whether a prefetch operation of the CXL device is completed (a storage operation status holding unit holds the prefetch operation status signal, which is information indicating whether or not the prefetch operation has been completed Paragraph [0138]).
KB and Tanaka et al., hereinafter KBT, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KBT before the effective filing date of the invention, to modify the teachings of KB by including information indicating whether a prefetch operation of the CXL device is completed, as taught by Tanaka et al.
One of ordinary skill in the art would have been motivated to include information indicating whether a prefetch operation of the CXL device is completed so that other deices such as the master can be aware of the status of the external device that is in the process of executing a prefetch and can perform the optimum process based on the status Paragraph [0238].
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over KB in further view of Narsale et al. (US 2022/0019536 A1) hereinafter Narsale et al.
Regarding claim 6, KB teaches all of the features with respect to claim 3 as outlined above.
Kwon et al. further teaches wherein the CXL.io module is further configured to: receive the prefetch request from the host device according to a CXL.io protocol (prefetch decision circuit receives a request from host device Paragraph [0048] connected via CXL interface Paragraph [0043]. Note that Bert et al. explains that CXL.io. is a protocol used for storage access [0016]).
KB does not appear to explicitly teach, however, Narsale et al. teaches based on a prefetch management capability of the CXL device being set in accordance with the prefetch request, transmit at least one prefetch indicator corresponding to the prefetch request from among the plurality of prefetch indicators to the prefetch module (the processor receives an instruction to the interface bridge as to whether to enable or disable prefetch of data (i.e., the claimed prefetch management capability) to the prefetch buffers Paragraph [0066], where the prefetch request incudes a memory address Paragraph [0042]).
KB and Narsale et al., hereinafter KBN, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KBN before the effective filing date of the invention, to modify the teachings of KB by including based on a prefetch management capability of the CXL device being set in accordance with the prefetch request, transmit a prefetch indicator corresponding to the prefetch request to the prefetch module, as taught by Narsale et al.
One of ordinary skill in the art would have been motivated to include based on a prefetch management capability of the CXL device being set in accordance with the prefetch request, transmit a prefetch indicator corresponding to the prefetch request to the prefetch module such that the host system can determine to enable/disable prefetching based on the type of access (sequential vs. random reads) [0066].
Regarding claim 7, KBN teaches all of the features with respect to claim 6 as outlined above.
Kwon et al. further teaches wherein the prefetch module is further configured to: prefetch the first data from the memory device using the memory controller based on the prefetch indicator received from the CXL.io module, and store the prefetched first data (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over KB in further view of Gschwind et al. (US 2017/0132133 A1) hereinafter Gschwind et al.
Regarding claim 8, KB teaches all of the features with respect to claim 2 as outlined above.
KB does not appear to explicitly teach, however, Gschwind et al. teaches wherein the CXL.mem module further comprises a decoder configured to: decode the prefetch request in order to extract the prefetch indicator, and transmit the extracted prefetch indicator to the prefetch module (address decode 2211 decodes the address of a prefetch operation and asserts the target address of a prefetch read operation is on a prefetch read address bus 2203 Paragraph [0208], [0213]).
KB and Gschwind et al., hereinafter KBG, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KBG before the effective filing date of the invention, to modify the teachings of KB by including a decoder configured to: decode the prefetch request in order to extract the prefetch indicator, and transmit the extracted prefetch indicator to the prefetch module, as taught by Gschwind et al.
One of ordinary skill in the art would have been motivated to include a decoder configured to: decode the prefetch request in order to extract the prefetch indicator and transmit the extracted prefetch indicator to the prefetch module to determine the target address to send via the prefetch read address bus.
Regarding claim 9, KBG teaches all of the features with respect to claim 8 as outlined above.
Gschwind et al. further teaches wherein the prefetch request comprises a plurality of fields, and wherein at least one field from among the plurality of fields comprises information about the prefetch indicator (Fig. 6 shows a read request has a plurality of fields 3301-3306, including p information field 3304 which specifies whether the read request is a prefetch request and address field 3305 and CRC info field 3306 Paragraph [0221]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KBG in further view of Sano et al. (US 2024/0345774 A1) hereinafter Sano et al.
Regarding claim 10, KBG teaches all of the features with respect to claim 9 as outlined above.
Gschwind et al. further teaches wherein the prefetch indicator comprises prefetch request information (Fig. 6 shows a read request has a plurality of fields 3301-3306, including p information field 3304 which specifies whether the read request is a prefetch request Paragraph [0221]).
KBG does not appear to explicitly teach, however, Sano et al. teaches wherein the prefetch indicator comprises prefetch data size information (a prefetch request is written to the request queue with the address and size information indicating the size of data to be prefetched Paragraph [0069]).
KBG and Sano et al., hereinafter KBGS, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KBGS before the effective filing date of the invention, to modify the teachings of KBG by including prefetch data size information in the request, as taught by Gschwind et al.
One of ordinary skill in the art would have been motivated to include prefetch data size information in the request such that prefetching the target data is performed based on the data size and make prefetching more efficient [0069].
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narsale et al. (US 2022/0019536 A1) hereinafter Narsale et al. in view of Kwon et al. in further view of Bert et al.
Regarding claim 11, Narsale et al. teaches a device, comprising:
a first module configured to set a prefetch management capability based on a first request received from a host device (the interface bridge receives an instruction from a first device to enable or disable prefetching of data to the set of prefetch buffers, for example, host system can sent an instruction to the memory sub-system to enable prefetching of data Paragraph [0066]);
a memory controller configured to access a memory device; and a second module configured to:
receive at least one prefetch indicator from the first module based on the prefetch management capability being set by the first module, and prefetch first data corresponding to the at least one prefetch indicator using the memory controller (interface bridge responds to a request of operation by determine, based on the received memory address, whether the request results in read hit and then prefetches data from the second device Paragraphs [0052]-[0053]), and
store the prefetched first data, wherein the at least one prefetch indicator comprises address information about a prefetch region in which the first data is stored (the interface bridge prefetches second data from the second device based on a prefetch policy and determining that the data is stored on the second device at a set of data storage locations corresponding to a set of sequential memory addresses Paragraph [0060]), and at least one of prefetch control information and prefetch status information, and wherein the second module is further configured to output the first data stored in the second module to the host device based on an address of requested data associated with a data access request from the host device belonging to the prefetch region (the interface bridge responds to the request of operation by determining whether existing data is currently stored on the set of prefetch buffers in association with the memory address Paragraphs [0067]-[0068]).
Narsale et al. does not appear to explicitly teach, however, Kwon et al. teaches wherein the device is a Compute Express Link (CXL) device comprising a CXL.io module (memory expanding device 200 is connected to host device 100 and memory device 220 via compute express link (CXL) interface Paragraph [0043]) and the request is a CXL.io request received from a host device, and further teaches a CXL.mem module configured to: receive at least one prefetch indicator from the CXL.io module, prefetch first data, and output first data (prefetch decision circuit receives a request from host device Paragraph [0048] connected via CXL interface Paragraph [0043], where prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]).
Narsale et al. and Kwon et al., hereinafter NK, are analogous art to the claimed invention because they are in the same field of prefetching in a memory system. Because both NK teach the use of prefetching data using various data protocols (ex. PCIe protocol of Narsale), it would have been obvious to one skilled in the art to substitute one type of memory protocol for another to achieve the predictable result of sending and retrieving data using a particular type of protocol as disclosed by Kwon et al., in this case, CXL (KSR, MPEP 2143).
NK does not appear to explicitly teach, however, Bert et al. teaches to at least one of prefetch control information and prefetch status information (storage memory page ID identifies a page of the memory space and page status 171 of address map, see Fig. 4 Paragraphs [0149]-[0150]).
NK and Bert, hereinafter NKB, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of NKB before the effective filing date of the invention, to modify the teachings of NK by including prefetch control information or prefetch status information.
One of ordinary skill in the art would have been motivated to include prefetch control information or prefetch status information to be able to identify the dynamic correlation between prefetched information as well as process data according to the status of its page.
Regarding claim 12, NKB teaches all of the features with respect to claim 11 as outlined above.
Kwon et al. further teaches wherein the CXL.mem module comprises: a prefetch memory configured to store a plurality of first data corresponding to at least one slot (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]); and a prefetch controller configured to: store at least one address associated with the prefetch region in a lookup table (the prefetch decision circuit stores a program counter and memory address, where the memory address is an address in which data required by the host device is stored within the memory expanding device Paragraph [0056]- [0057], [0066]. Note that Bert et al. teaches the memory sub-system 110 manages an address map which is the lookup table Paragraphs [0114], [0118]-[0121]).
Narsale et al. further teaches control a prefetch operation according to the setting of the prefetch management capability (the interface bridge receives an instruction from a first device to enable or disable prefetching of data to the set of prefetch buffers, for example, host system can sent an instruction to the memory sub-system to enable prefetching of data Paragraph [0066]).
Regarding claim 13, NKB teaches all of the features with respect to claim 12 as outlined above.
Kwon et al. further teaches wherein the CXL.mem module is further configured to: read the address from the prefetch memory, and output the first data corresponding to the address to the host device based on the address being included in the at least one address stored in the lookup table (the prefetch decision circuit stores a program counter and memory address, where the memory address is an address in which data required by the host device is stored within the memory expanding device Paragraph [0056], and when a cache hit occurs in the cache controller, the prefetch support circuit transmits the cache hit info and prefetch info to the memory expanding device to be retrieved through a root complex and stored inside the prefetch buffer Paragraph [0057], [0066]. Note that Bert et al. teaches the memory sub-system 110 manages this information in an address map which is the lookup table Paragraphs [0114], [0118]-[0121]).
Regarding claim 14, NKB teaches all of the features with respect to claim 12 as outlined above.
Narsale et al. further teaches wherein the CXL.mem module is further configured to transmit the at least one prefetch indicator to the prefetch controller according to the setting of the prefetch management capability (the interface bridge receives an instruction from a first device to enable prefetching of data to the set of prefetch buffers, for example, host system can sent an instruction to the memory sub-system to enable prefetching of data Paragraph [0066] and in response, interface bridge responds to a request of operation by determine, based on the received memory address, whether the request results in read hit and then prefetches data from the second device Paragraphs [0052]-[0053]) and Bert et al. teaches the CXL.io module comprises a plurality of slots mapped to a plurality of prefetch indicators (storage memory page ID identifies a page of the memory space and page status 171 of address map, see Fig. 4 Paragraphs [0149]-[0150]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over NKB in further view of Tanaka et al. (US 2010/0318707 A1) hereinafter Tanaka et al.
Regarding claim 15, NKB teaches all of the features with respect to claim 11 as outlined above.
NKB does not appear to explicitly teach, however, Tanaka et al. teaches wherein the at least one of prefetch control information and prefetch status information comprises information about whether a prefetch request is received from the host device for each slot from among a plurality of slots included in the CXL.io module, and whether a prefetch operation of the CXL device is completed (a storage operation status holding unit holds the prefetch operation status signal, which is information indicating whether or not the prefetch operation has been completed Paragraph [0138]).
NKB and Tanaka et al., hereinafter NKBT, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of NKBT before the effective filing date of the invention, to modify the teachings of NKB by including information indicating whether a prefetch operation of the CXL device is completed, as taught by Tanaka et al.
One of ordinary skill in the art would have been motivated to include information indicating whether a prefetch operation of the CXL device is completed so that other deices such as the master can be aware of the status of the external device that is in the process of executing a prefetch and can perform the optimum process based on the status Paragraph [0238].
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. in view of Gschwind et al. in further view of Sano et al.
Regarding claim 16, Kwon et al. teaches a Compute Express Link (CXL) device, comprising:
a memory controller connected to a memory device in order to perform data access (memory controller 210 may control the overall operation of the memory expanding device and includes the prefetch decision circuit Paragraph [0070]); and a CXL.mem module configured to:
receive a CXL.mem request from a host device (host device includes a prefetch support circuit which generates prefetch information required to prefetch data and transmit the prefetch information to the memory expanding device Paragraph [0045]),
based on a prefetch indicator corresponding to pre-stored first data being included in a CXL.mem request, prefetching the first data from the memory device using the memory controller (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]),
wherein the prefetch indicator comprises prefetch request field information (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information Paragraph [0074]-[0075]).
Kwon et al. does not appear to explicitly teach, however, Gschwind et al. teaches to decode the CXL.mem request (address decode 2211 decodes the address of a prefetch operation and asserts the target address of a prefetch read operation is on a prefetch read address bus 2203 Paragraph [0208], [0213]).
Kwon and Gschwind et al., hereinafter KG, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KG before the effective filing date of the invention, to modify the teachings of Kwon et al. by including a decoder configured to: decode the prefetch request in order to extract the prefetch indicator, and transmit the extracted prefetch indicator to the prefetch module, as taught by Gschwind et al.
One of ordinary skill in the art would have been motivated to include a decoder configured to: decode the prefetch request in order to extract the prefetch indicator and transmit the extracted prefetch indicator to the prefetch module to determine the target address to send via the prefetch read address bus.
KG does not appear to explicitly teach, however, Sano et al. teaches wherein the prefetch indicator comprises prefetch data size field information (a prefetch request is written to the request queue with the address and size information indicating the size of data to be prefetched Paragraph [0069]).
KG and Sano et al., hereinafter KGS, teach prefetching in memory systems, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of KGS before the effective filing date of the invention, to modify the teachings of KG by including prefetch data size information in the request, as taught by Gschwind et al.
One of ordinary skill in the art would have been motivated to include prefetch data size information in the request such that prefetching the target data is performed based on the data size and make prefetching more efficient [0069].
Regarding claim 17, KGS teaches all of the features with respect to claim 16 as outlined above.
Sano et al. further teaches wherein the CXL.mem module is further configured to: check a prefetch region up to an address having a size corresponding to the prefetch data size field information based on a base address included in the CXL.nem request, and read the first data by accessing the prefetch region of the memory device (in addition to the address of the request, the prefetch request further includes a data size (i.e., size information indicating the size of the data to be prefetched Paragraph [0069], [0067]).
Claim(s) 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over KGS in further view of Onishi et al. (US 2024/0319891 A1) hereinafter Onishi et al.
Regarding claim 18, KGS teaches all of the features with respect to claim 16 as outlined above.
Bert et al. teaches wherein the CXL.mem module comprises: a prefetch controller configured to: store a lookup table including data mapping information associated with a prefetch region corresponding to the prefetch indicator (the memory sub-system 110 manages an address map 155 identifying the correlations between pages 177 of the cache memory and pages 167 of storage memory in the loadable portion Paragraph [0114], where the storage memory page ID 165 identifies a corresponding memory address which identifies a storage location of the memory cells Paragraphs [0118]-[0121]) and Kwon et al. teaches transmit an access request associated with the prefetch region to the memory controller, and fetch the first data associated with the prefetch region from the memory controller; and a prefetch memory configured to store the fetched first data (prefetch decision circuit may prefetch data from the prefetch address determined based on the prefetch information and store the prefetch address and prefetch data therein Paragraph [0074]-[0075]) and Gschwind et al. further teaches a decoder configured to decode the CXL.mem request received from the host device in order to extract the prefetch indicator (address decode 2211 decodes the address of a prefetch operation and asserts the target address of a prefetch read operation is on a prefetch read address bus 2203 Paragraph [0208], [0213]).
KGS does not appear to explicitly teach, however, Onishi et al. teaches the decoder is a host-managed device memory decoder configured to decode (the system decoder corresponds to a host-managed device memory (HDM) decoder in CXL.20 Paragraph [0059]-[0060]).
KGS and Onishi et al., hereinafter KGSO, are analogous art to the claimed invention because they are in the same field of prefetching in a memory system. Because both KGSO teach the use of decoding data (ex. using a device-side address decoder of Gschwind et al.), it would have been obvious to one skilled in the art to substitute one type of decoder for another to achieve the predictable result of decoding data as disclosed by Onishi et al., in this case, a host-managed device memory decoder (KSR, MPEP 2143).
Regarding claim 20, KGSO teaches all of the features with respect to claim 18 as outlined above.
Kwon et al. teaches the CXL.mem module is further configured to: read, from the prefetch memory, an address of requested data corresponding to the access request received from the host device, and based on the address being included in the prefetch region stored in the lookup table, output the first data corresponding to the address to the host device (the prefetch decision circuit stores a program counter and memory address, where the memory address is an address in which data required by the host device is stored within the memory expanding device Paragraph [0056], and when a cache hit occurs in the cache controller, the prefetch support circuit transmits the cache hit info and prefetch info to the memory expanding device to be retrieved through a root complex and stored inside the prefetch buffer Paragraph [0057], [0066]. Note that Bert et al. teaches the memory sub-system 110 manages this information in an address map which is the lookup table Paragraphs [0114], [0118]-[0121]).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically regarding claim 19, “wherein the prefetch controller is further configured to: based on a slot associated with the prefetch indicator being already used in the prefetch memory, flush data mapped to the prefetch indicator to the memory device through the memory controller, and prefetch new first data corresponding to the decoded prefetch indicator from the memory device to the slot in the prefetch memory,” is not taught by the prior art. While the prior art KGSO does teach prefetching new data corresponding to a decoded prefetch indicator, the prior art is silent with regards to flushing data mapped to the prefetch indicator based on a slot associated with the prefetch indicator being already used in the prefetch memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 2024/0070073 A1) teaches a CXL memory expander application-specific integrated circuit (ASIC) chip which connects processor to CXL memory, and a cache that is configured to cache the data obtained from the external CXL memory
Walker et al. (US 2004/0199728 A1) teaches a memory request includes a source identifier that unique identifies the processor (i.e., host) that generated the request.
Pham et al. (US 2025/0077435) teaches an adaptive prefetch that includes predicting an address of the next page.
Lee et al. (US 2022/0121574 A1) teaches accessing a device-attached memory using CXL protocols, such as CXL.io and CXL.mem.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
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