Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takagi (US 2002/0017962 A1, hereinafter “Takagi”).
As to claim 5, Takagi (Fig. 5) discloses a clock generator (3) comprising:
a first clock generation circuit (2) configured to output a clock (S3), data synchronized with the clock (S2; Para. 0085), and a timing control signal (S1) each in serial transmission;
a second clock generation circuit (Fig. 6 element 1) connected to the first clock generation circuit and configured to count the clock based on the data (S6; Para. 0081) and cause a pulse of pre-clocks to rise and fall to generate the pre-clocks (S7) in which phases are sequentially shifted based on the data and the clock (Fig. 7C; Para. 0085-0086, disenable phase S1 would shift the phase of S7); and
a clock adjustment circuit configured to adjust at least one of a rising time point, a pulse width, or a falling time point of a pulse of a pre-clock based on the timing control signal (Para. 0086), wherein:
a frequency of each of the timing control signal (Fig. 7C element S1) and the pre-clocks (S6) is lower than a frequency of the clock (Fig. 7B element S3) and the data (Fig. 7A element S2; Para 0086, “pulse width data S7 is outputted after enable signal S1 changes from enable state to disenable state and a preset number of clock signals are input”),
the timing control signal (Fig. 7A) includes at least one pulse overlapped with any one of the pre- clocks (Para. 0086, pulse is interpreted to read on a period of signal including enable and disenable).
As to claim 7, Takagi (Fig. 7C) discloses the clock generator according to claim 5, wherein the pulse of the timing control signal (S1) overlaps with at least one of the rising time point or the falling time point of the pulse of the pre-clock (Para. 0086).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Kuroiwa et al. (US 2017/0315659 A1, hereinafter “Kuroiwa”).
As to claim 1, Takagi (Fig. 5) discloses a clock generator comprising:
a first clock generation circuit (3) configured to generate a clock (S3) and data synchronized with the clock (S2; Para. 0060, 0071);
a first wiring (“wire” for clock) connected to the first clock generation circuit to transmit the clock;
a second wiring (“wire” for SO) connected to the first clock generation circuit to transmit the data (S2); and
a second clock generation circuit (Fig. 4 element 1) connected to the first clock generation circuit (3) through the first wiring (“wire” for clock) and the second wiring (“wire for SO) and configured to count the clock based on the data and cause a pulse of output clocks to rise and fall to generate the output clocks (S7) in which phases are sequentially shifted based on the data and the clock (Fig. 7C; Para. 0085-0086, disenable phase S1 would shift the phase of S7).
Takagi does not disclose wherein the first clock generation circuit is configured to vary one or more of a pulse rising time point of a pulse of the clock or a pulse falling time point of the pulse of the clock within one clock cycle of the clock, and
wherein the first clock generation circuit is configured to fix the one clock cycle of the clock, and vary a first time from a start time to a rising time of the one clock cycle and a second time from a falling time to an end time of the one clock cycle within the fixed one clock cycle.
However, Kuroiwa (Fig. 1) teaches wherein the first clock generation circuit (26) is configured to vary one or more of a pulse rising time point of a pulse of the clock or a pulse falling time point of the pulse of the clock within one clock cycle of the clock (Fig. 16-17; Para. 0114-0116), and
wherein the first clock generation circuit is configured to fix the one clock cycle of the clock (Fig. 16 element Tmg1-1), and vary a first time from a start time to a rising time of the one clock cycle (rising time of Tmg1-1) and a second time from a falling time to an end time of the one clock cycle within the fixed one clock cycle (falling time of Tmg1-1; Para. 0116, clock cycles for different frame modes).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kuroiwa to adjust the clock cycle in the device disclosed by Takagi. The motivation would have been to reduce the flicker phenomenon (Kuroiwa; Para. 0017).
As to claim 2, Takagi in view of Kuroiwa disclose the clock generator of claim 1. Kuroiwa (Fig. 17) further teaches wherein the clock (Tmg1-2) rises at a time point delayed by the first time (time period between Tmg2 and rising point of Tmg1-2), and the output clock falls at a time point ahead by the second time (Tmg3).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Takagi as applied to claim 5 above, and further in view of Kim et al. (US 2022/0028320 A1, hereinafter “Kim”).
As to claim 6, Takagi does not disclose the clock generator of claim 5, wherein the second clock generation circuit is configured to separate pulses of the timing control signal that are serially received by the second clock generation circuit into a plurality of parallel timing control signals corresponding to the pre- clocks, respectively.
However, Kim teaches wherein the second clock generation circuit is configured to separate pulses of the timing control signal that are serially received by the second clock generation circuit into a plurality of parallel timing control signals corresponding to the pre- clocks, respectively (Para. 0130).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kim to convert serial signals into parallel signals in the device disclosed by Takagi. The motivation would have been to transmit/process the signals as necessary (Kim; Para. 130).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Takagi as applied to claim 7 above, and further in view of Kawagoshi et al. (US 2008/0136805 A1, hereinafter “Kawagoshi”).
As to claim 8, Takagi does not disclose the clock generator according to claim 7, wherein a pulse width of the timing control signal is smaller than a pulse width of the pulse of the pre-clock.
However, Kawagoshi (Fig. 5) teaches wherein a pulse width of the timing control signal (SCA) is smaller than a pulse width of the pulse of the pre-clock (CLK; Para. 0062).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kawagoshi to have different pulse width for the different signals in the device disclosed by Takagi. The motivation would have been to reduce the noise during display driving (Kawagoshi; Para. 0027).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Takagi as applied to claim 5 above, and further in view of Jeong et al. (US 2017/0116914 A1, hereinafter ”Jeong”).
As to claim 13, Takagi does not disclose the clock generator according to claim 5, further comprising: an output buffer configured to increase a swing width of the output clock, wherein the clock adjustment circuit and the output buffer are included in the second clock generation circuit.
However, Jeong teaches further comprising: an output buffer configured to increase a swing width of the output clock, wherein the clock adjustment circuit and the output buffer are included in the second clock generation circuit (Para. 0045).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Jeong to add an output buffer in the device disclosed by Takagi. The motivation would have been to provide a swing width suitable for operation of the thin film transistors of pixels (Jeong; Para. 0045).
Allowable Subject Matter
Claims 3-4 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 3, The prior art does not disclose the limitations “a second clock generation circuit connected to the first clock generation circuit through the first wiring and the second wiring and configured to count the clock based on the data and cause a pulse of output clocks to rise and fall to generate the output clocks in which phases are sequentially shifted based on the data and the clock” when combined with other limitations.
Claims 9-12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Jang et al. (US 2021/0020137 A1) discloses a level shifter connected to the gate driver and data driver (Fig 7B element 141).
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/Examiner, Art Unit 2625