DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-19 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DISPLAY PANEL HAVING MODE SELECTOR FOR SWITCHING VIEWING ANGLES AND DISPLAY DEVICE INCLUDING THE SAME.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0257769 A1) in view of Kwon et al. (US 2025/0316230 A1).
As to claim 1, Kim teaches a display panel (Kim, FIG. 1, [0047], “display panel 110”) comprising:
a plurality of data lines (Kim, FIG. 2, [0049], “data lines DL”), a plurality of gate lines (Kim, FIG. 2, [0049], “gate lines GL”), a plurality of power lines (Kim, FIGS. 2-3, [0051], “power supply voltage supply lines PL”), a plurality of mode selection lines (Kim, FIG. 3, [0067], “first mode signal S(k)” and “second mode signal P(k)”), and a plurality of sub-pixels (Kim, FIG. 2, [0048], sub-pixels in “pixel areas PX”), wherein each of the sub-pixels (Kim, FIG. 2, [0048], sub-pixels in “pixel areas PX”) comprises:
a first light-emitting element (Kim, FIG. 3, [0066], “first light emitting element 310”);
a second light-emitting element (Kim, FIG. 3, [0066], “second light emitting element 320”);
a first driver (Kim, e.g., FIG. 16, [0216], “data drivers 130-1 to 130-3”) connected to a first data line (Kim, e.g., FIG. 16, [0216], data line corresponding to “first area 1001 driven in the first mode”);
a second driver (Kim, FIG. 10, [0216], “second data drivers 130-4 to 130-6”) connected to a second data line (Kim, e.g., FIG. 16, [0216], data line corresponding to “second area 1002 driven in the second mode”); and
a mode selector (Kim, FIG. 12, [0179], “mode controller 1200”) connected to the first driver (Kim, e.g., FIG. 16, [0216], “data drivers 130-1 to 130-3”), the second driver (Kim, FIG. 10, [0216], “second data drivers 130-4 to 130-6”), the first light-emitting element, the second light-emitting element (Kim, see FIG. 12, [0179], e.g., “the first area 1001 of the display panel 110 can operate in the first mode and the second area 1002 can operate in the second mode”), and the plurality of mode selection lines to which mode selection signals are configured to be applied (Kim, FIG. 12, [0181], “the mode controller 1200 can provide a low-level of the first mode signal and a high-level of the second mode signal to the pixel circuit disposed in the first area 1001. The mode controller 1200 can provide a low-level of the second mode signal and a high-level of the first mode signal to the pixel circuit disposed in the second area 1002”).
Kim does not teach a first driver … “to which a first data voltage is configured to be applied and gate lines to which gate signals are configured to be applied”; and a second driver … “to which a second data voltage is configured to be applied and the gate lines to which the gate signals are configured to be applied”.
However, Kwon teaches the concept of a first driver … to which a first data voltage (Kwon, e.g., FIG. 1, [0078], “first data voltages VDAT1 based on the first gamma reference voltages VGMA1 corresponding to the first mode”) is configured to be applied and gate lines to which gate signals (Kwon, e.g., FIG. 1, [0055], “scan signals SS”) are configured to be applied (Kwon, see FIG. 1); and
a second driver … to which a second data voltage (Kwon, e.g., FIG. 1, [0079], “second data voltages VDAT2 based on the second gamma reference voltages VGMA2 corresponding to the second mode”) is configured to be applied and the gate lines to which the gate signals (Kwon, e.g., FIG. 1, [0055], “scan signals SS”) are configured to be applied (Kwon, see FIG. 1).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify “data driver 130” taught by Kim to further comprise generate “VDAT1” corresponding to the “1st (public) mode” and “VDAT2” corresponding to the “2nd (private) mode”, as taught by Kwon, in order to provide “a display device capable of providing seamless mode switching” (Kwon, [0005]).
As to claim 2, Kim teaches the display panel of claim 1, further comprising:
a wide viewing angle lens (Kim, see FIG. 8, [0133], “first lenses 510”; [0134], “first lens areas BWE of the pixel area PA can be used to provide a wide viewing angle for a first mode (e.g., a sharing mode)”) overlapping with an emission area of the first light-emitting element (Kim, see FIG. 8, [0133], “light generated by the first light emitting element 310 of each pixel area PA can be emitted through the first lens 510 of the corresponding pixel area PA”); and
a narrow viewing angle lens (Kim, see FIG. 9, [0135], “second lenses 520”; “the second lens areas BNE, RNE, and GNE of the pixel area PA can be used to provide a narrow viewing angle for a second mode (e.g., a private viewing mode, a privacy mode, or a low distraction viewing mode, etc.)”) overlapping with an emission area of the second light-emitting element (Kim, FIG. 9, [0135], “light generated by the second light emitting element 320 of the pixel area PA can be emitted through the second lens 520 in the pixel area PA”).
As to claim 3, Kim teaches the display panel of claim 1, wherein the first driver (Kim, FIG. 6, [0098], “pixel circuit 600”) comprises:
a first driving element (Kim, FIG. 6, “DT”) including a first electrode connected to a first node (Kim, FIG. 6, node at “power supply line 517”), a gate electrode connected to a second node (Kim, FIG. 6, node on “C1”), and a second electrode connected to a third node (Kim, FIG. 6, node between “DT” and “T7”);
a first capacitor (Kim, FIG. 6, “C1”) connected between the second node (Kim, FIG. 6, node on “C1”) and a fourth node (Kim, FIG. 6, node between “C1” and “T6”);
a first switching element (Kim, FIG. 6, “T5”) connected between the second node (Kim, FIG. 6, node on “C1”) and the third node (Kim, FIG. 6, node between “DT” and “T7”);
a second switching element (Kim, FIG. 6, “T6”) connected between the first data line (Kim, FIG. 6, “Vdata”) and the fourth node (Kim, FIG. 6, node between “C1” and “T6”);
a third switching element (Kim, FIG. 6, “T3”) connected between the fourth node (Kim, FIG. 6, node between “C1” and “T6”) and a third power line (Kim, FIG. 6, “reference voltage line 511”);
a fourth switching element (Kim, FIG. 6, “T7”) connected between the third node (Kim, FIG. 6, node between “DT” and “T7”) and a fifth node (Kim, FIG. 6, node between “T7” and “T1”);
a fifth switching element (Kim, FIG. 6, “T41”) connected between the third power line (Kim, FIG. 6, “reference voltage line 511”) and the fifth node (Kim, FIG. 6, node between “T7” and “T1”); and
a sixth switching element (Kim, FIG. 6, “T42”) connected between the third power line (Kim, FIG. 6, “reference voltage line 511”) and an anode electrode of the second light-emitting element (Kim, FIG. 6, anode of “ED2”), wherein the first node (Kim, FIG. 6, node at “power supply line 517”) is connected to a first power line (Kim, FIG. 6, “power supply line 517”).
As to claim 4, Kim teaches the display panel of claim 3, wherein the second driver comprises: a second driving element including a first electrode connected to the first node, a gate electrode connected to a sixth node, and a second electrode connected to a seventh node; a second capacitor connected between the sixth node and an eighth node; a seventh switching element connected between the sixth node and the seventh node; an eighth switching element connected between the second data line and the eighth node; a ninth switching element connected between the eighth node and the third power line; and a tenth switching element connected between the seventh node and a ninth node (Kim, see FIG. 6: claim 4 recites the “second driver” shown in FIGS. 3-4 of the present application, which is a mirror image of the “first driver” recited in claim 3, which in turn a mirror image of the circuit of FIG. 6 of Kim. Kim teaches them, and please see claim 3 for detailed analysis).
As to claim 6, Kim in view of Kwon teaches a display device (Kim, FIG. 1, [0044], “display device 100”) comprising:
a display panel (Kim, FIG. 1, [0047], “display panel 110”) comprising a plurality of data lines (Kim, FIG. 2, [0049], “data lines DL”), a plurality of gate lines (Kim, FIG. 2, [0049], “gate lines GL”), a plurality of power lines (Kim, FIGS. 2-3, [0051], “power supply voltage supply lines PL”), a plurality of mode selection lines (Kim, FIG. 3, [0067], “first mode signal S(k)” and “second mode signal P(k)”), and a plurality of sub-pixels (Kim, FIG. 2, [0048], sub-pixels in “pixel areas PX”);
a data driver (Kwon, FIG. 1, [0047], “data driver 140”) configured to output a first data voltage (Kwon, e.g., FIG. 1, [0078], “first data voltages VDAT1 based on the first gamma reference voltages VGMA1 corresponding to the first mode”) and a second data voltage (Kwon, e.g., FIG. 1, [0079], “second data voltages VDAT2 based on the second gamma reference voltages VGMA2 corresponding to the second mode”); and
a gate driver (Kim, FIG. 2, [0054], “gate driver 120”) configured to output a first scan signal (Kim, FIG. 5, [0094], “Scan2(n)” on “first scan line 513”), a second scan signal (Kim, FIG. 5, [0094], “Scan1(n)” on “second scan line 518”), a first emission signal (Kim, FIG. 5, [0100], “emission signal EM(n)”), and a second emission signal (Kwon, e.g., FIG. 1, [0074], “ emission signals EM”), wherein each of the sub-pixels (Kim, FIG. 2, [0048], sub-pixels in “pixel areas PX”) comprises:
a first light-emitting element (Kim, FIG. 3, [0066], “first light emitting element 310”);
a second light-emitting element (Kim, FIG. 3, [0066], “second light emitting element 320”);
a first driver (Kim, e.g., FIG. 16, [0216], “data drivers 130-1 to 130-3”) connected to a first data line (Kim, e.g., FIG. 16, [0216], data line corresponding to “first area 1001 driven in the first mode”) to which the first data voltage (Kwon, e.g., FIG. 1, [0078], “first data voltages VDAT1 based on the first gamma reference voltages VGMA1 corresponding to the first mode”) is configured to be applied and gate lines (Kim, FIG. 2, [0049], “gate lines GL”) to which the first scan signal (Kim, FIG. 5, [0094], “Scan2(n)” on “first scan line 513”), the second scan signal (Kim, FIG. 5, [0094], “Scan1(n)” on “second scan line 518”), the first emission signal (Kim, FIG. 5, [0100], “emission signal EM(n)”), and the second emission signal (Kwon, e.g., FIG. 1, [0074], “emission signals EM”) are configured to be applied (Kwon, e.g., see FIG. 16);
a second driver (Kim, FIG. 10, [0216], “second data drivers 130-4 to 130-6”) connected to a second data line (Kim, e.g., FIG. 16, [0216], data line corresponding to “second area 1002 driven in the second mode”) to which the second data voltage (Kwon, e.g., FIG. 1, [0079], “second data voltages VDAT2 based on the second gamma reference voltages VGMA2 corresponding to the second mode”) is configured to be applied and gate lines (Kim, FIG. 2, [0049], “gate lines GL”) to which the first scan signal (Kim, FIG. 5, [0094], “Scan2(n)” on “first scan line 513”), the second scan signal (Kim, FIG. 5, [0094], “Scan1(n)” on “second scan line 518”), the first emission signal (Kim, FIG. 5, [0100], “emission signal EM(n)”), and the second emission signal (Kwon, e.g., FIG. 1, [0074], “emission signals EM”) are configured to be applied (Kwon, e.g., see FIG. 16); and
a mode selector (Kim, FIG. 12, [0179], “mode controller 1200”) connected to the first driver (Kim, e.g., FIG. 16, [0216], “data drivers 130-1 to 130-3”), the second driver (Kim, FIG. 10, [0216], “second data drivers 130-4 to 130-6”), the first light-emitting element, the second light-emitting element (Kim, see FIG. 12, [0179], e.g., “he first area 1001 of the display panel 110 can operate in the first mode and the second area 1002 can operate in the second mode”), and the plurality of mode selection lines to which mode selection signals are configured to be applied (Kim, FIG. 12, [0181], “the mode controller 1200 can provide a low-level of the first mode signal and a high-level of the second mode signal to the pixel circuit disposed in the first area 1001. The mode controller 1200 can provide a low-level of the second mode signal and a high-level of the first mode signal to the pixel circuit disposed in the second area 1002”). Examiner renders the same motivation as in claim 1.
As to claim 7, Kim teaches the display device of claim 6, wherein the first driver (Kim, FIG. 6, [0098], “pixel circuit 600”) comprises:
a first driving element (Kim, FIG. 6, “DT”) comprising a first electrode connected to a first node (Kim, FIG. 6, node at “power supply line 517”) to which a pixel driving voltage (Kim, FIG. 6, “ELVDD”) is applied, a gate electrode connected to a second node (Kim, FIG. 6, node on “C1”), and a second electrode connected to a third node (Kim, FIG. 6, node between “DT” and “T7”);
a first capacitor (Kim, FIG. 6, “C1”) connected between the second node (Kim, FIG. 6, node on “C1”) and a fourth node (Kim, FIG. 6, node between “C1” and “T6”);
a first switching element (Kim, FIG. 6, “T5”) connected between the second node (Kim, FIG. 6, node on “C1”) and the third node (Kim, FIG. 6, node between “DT” and “T7”), which turns on in response to a gate-on voltage of the first scan signal (Kim, FIG. 6, “Scan2(n)”);
a second switching element (Kim, FIG. 6, “T6”) connected between the first data line (Kim, FIG. 6, “Vdata”) and the fourth node (Kim, FIG. 6, node between “C1” and “T6”), which turns on in response to a gate-on voltage of the second scan signal (Kim, FIG. 6, “Scan1(n)”);
a third switching element (Kim, FIG. 6, “T3”) connected between the fourth node (Kim, FIG. 6, node between “C1” and “T6”) and a third power line (Kim, FIG. 6, “reference voltage line 511”) to which a reference voltage (Kim, FIG. 6, “Vref”) is applied, which turns on in response to a gate-on voltage of the first emission signal (Kim, FIG. 6, “EM(n)”);
a fourth switching element (Kim, FIG. 6, “T7”) connected between the third node (Kim, FIG. 6, node between “DT” and “T7”) and a fifth node (Kim, FIG. 6, node between “T7” and “T1”), which turns on in response to a gate-on voltage of the first emission signal (Kim, FIG. 6, “EM(n)”);
a fifth switching element (Kim, FIG. 6, “T41”) connected between the third power line (Kim, FIG. 6, “reference voltage line 511”) and the fifth node (Kim, FIG. 6, node between “T7” and “T1”), which turns on in response to a gate-on voltage of the first scan signal (Kim, FIG. 6, “Scan2(n)”); and
a sixth switching element (Kim, FIG. 6, “T42”) connected between the third power line (Kim, FIG. 6, “reference voltage line 511”) and an anode electrode of the second light-emitting element (Kim, FIG. 6, anode of “ED2”), which turns on in response to a gate-on voltage of the first scan signal (Kim, FIG. 6, “Scan2(n)”).
As to claim 8, Kim teaches the display device of claim 7, wherein the second driver comprises: a second driving element including a first electrode connected to the first node, a gate electrode connected to a sixth node, and a second electrode connected to a seventh node; a second capacitor connected between the sixth node and an eighth node; a seventh switching element connected between the sixth node and the seventh node, which turns on in response to a gate-on voltage of the first scan signal; an eighth switching element connected between the second data line and the eighth node, which turns on in response to a gate-on voltage of the second scan signal; a ninth switching element connected between the eighth node and the third power line, which turns on in response to a gate-on voltage of the second emission signal; and a tenth switching element connected between the seventh node and a ninth node, which turns on in response to a gate-on voltage of the second emission signal (Kim, see FIG. 6: claim 8 recites the “second driver” shown in FIGS. 3-4 of the present application, which is a mirror image of the “first driver” recited in claim 7, which in turn a mirror image of the circuit of FIG. 6 of Kim. Kim teaches them, and please see claim 7 for detailed analysis).
As to claim 18, Kim in view of Kwon teaches the display device of claim 6, wherein the data driver (Kwon, FIG. 8, [0084], “data driver 140”) is configured to output the data voltage corresponding to pixel data and to simultaneously output a specific gray voltage set regardless of the pixel data (Kwon, e.g., FIG. 8, [0083], “data driver 140 may sequentially provide the second data voltages VDAT2 to the plurality of pixels PX on the row-by-row basis by generating the second data voltages VDAT2 based on the second gamma reference voltages VGMA2”; [0084], “in the first mode switching frame period MSFP1 between the first mode MODE1 and the second mode MODE2, not only the second data voltages VDAT2 generated based on the second gamma reference voltages VGMA2 may be sequentially provided to the plurality of pixel rows PXR1, PXR2, PXR3, PXR4, etc. on the row-by-row basis”). Examiner renders the same motivation as in claim 1.
As to claim 19, Kim in view of Kwon teaches the display device of claim 6, wherein the data driver (Kwon, FIG. 8, [0084], “data driver 140”) is configured to output the data voltage corresponding to pixel data, and at the same time, some output terminals of the data driver are electrically separated from the data lines (Kwon, e.g., FIG. 8, [0084], “but also the first select signal SEL1 having the off-level and the second select signal SEL2 having the on-level may be sequentially provided to the plurality of pixel rows PXR1, PXR2, PXR3, PXR4, etc. on the row-by-row basis”). Examiner renders the same motivation as in claim 1.
Allowable Subject Matter
Claims 5 and 9-17 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, Kim teaches the display panel of claim 4, wherein the mode selector comprises:
a twelfth switching element (Kim, FIG. 6, “T1”) connected between the fifth node (Kim, FIG. 6, node between “T7” and “T1”) and an anode electrode of the first light-emitting element (Kim, FIG. 6, anode of “ED1”); and
a thirteenth switching element (Kim, FIG. 6, “T2”) connected between the ninth node (Kim, FIG. 6, node between “T2” and anode of “ED2”) and an anode electrode of the second light-emitting element (Kim, FIG. 6, anode of “ED2”), and
wherein cathode electrodes of the first and second light-emitting elements (Kim, FIG. 6, cathode electrodes of “ED1” and “ED2”) are connected to a second power line (Kim, FIG. 6, “power supply line 519”).
However, the closest known prior art, i.e., Kim et al. (US 2024/0257769 A1), Kwon et al. (US 2025/0316230 A1), Kim (US 2025/0246138 A1) and Shin et al. (US 2025/0252919 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “an eleventh switching element connected between the fifth node and the ninth node”.
As to claim 9, Kim teaches the display device of claim 8, wherein the mode selection signals include a first mode selection signal (Kim, FIG. 6, “P(k)”), a second mode selection signal (Kim, FIG. 6, “S(k)”), wherein the mode selector comprises:
a twelfth switching element (Kim, FIG. 6, “T1”) connected between the fifth node (Kim, FIG. 6, node between “T7” and “T1”) and an anode electrode of the first light-emitting element (Kim, FIG. 6, anode of “ED1”), which turns on in response to a gate-on voltage of the second mode selection signal (Kim, FIG. 6, “S(k)”); and
a thirteenth switching element (Kim, FIG. 6, “T2”) connected between the ninth node (Kim, FIG. 6, node between “T2” and anode of “ED2”) and an anode electrode of the second light-emitting element (Kim, FIG. 6, anode of “ED2”),
wherein cathode electrodes of the first and second light-emitting elements (Kim, FIG. 6, cathode electrodes of “ED1” and “ED2”) are connected to a second power line (Kim, FIG. 6, “power supply line 519”) to which a cathode voltage (Kim, FIG. 6, “ELVSS”) is applied, and
wherein each of the driving elements (Kim, FIG. 6, “DT”) and the switching elements (Kim, FIG. 6, “Tn”) comprises a transistor that turns on in response to the gate-on voltage and turns off in response to a gate-off voltage (Kim, see FIG. 6).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “a third mode selection signal”; “an eleventh switching element connected between the fifth node and the ninth node, which turns on in response to a gate-on voltage of the first mode selection signal”; and the thirteenth switching element … “which turns on in response to a gate-on voltage of the third mode selection signal”.
As to claims 10-17, they directly or indirectly depend from claim 9, and are allowable at least for the same reason above.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Kim (US 2025/0246138 A1) teaches the concept of “mode controller configured to generate a mode selection signal corresponding to a driving mode of the display panel” (Abs.); and Shin et al. (US 2025/0252919 A1) teaches the concepts of the “first and/or second driver of FIG. 4” (e.g., see FIG. 2A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Feb. 20, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2621
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