Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on February 24, 2026. U.S. patents and patent application publications, foreign patents and patent application publications, and non-patent literature documents have been considered.
Drawings
The drawings submitted on May 23, 2025 have been considered and accepted.
Specification
The specification submitted on May 23, 2025 has been considered and accepted.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected under the judicially created doctrine of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of copending Application 19218091. Although the claims at issue are not identical, they are not patentably distinct from each other because they represent obvious variations of the same core integrated circuit architecture.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding independent claims 1 and 9: Kumar claims an integrated circuit and a base die comprising: a host die disposed on an interposer; a base die disposed on the interposer; at least two high-bandwidth memory (HBM) stacks disposed on the base die that communicate with the host die; wherein the at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row; and a controller circuit operative to multiplex and demultiplex data (see Kumar claims 1 and 12).
The present application claims the exact same physical and spatial architecture (host die, base die, interposer, two HBM stacks arranged in a row with the host at one end). The claims differ from Kumar only in that the present claims recite compute circuitry disposed on the base die between the two HBM stacks to receive data and execute instructions from the host die, rather than reciting the multiplexing controller circuit.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the integrated circuit claimed in Kumar to include compute circuitry on the base die to execute instructions from the host. Integrating compute circuitry near memory (i.e., Compute-Near-Memory) is a known technique used to reduce data movement, lower latency, and conserve bandwidth between a host processor and memory stacks. Positioning this circuitry between the memory stacks constitutes an arrangement of known elements that yields the predictable result of minimizing trace lengths and maximizing shoreline efficiency on the base die.
Regarding independent claim 17: Kumar claims the above-described architecture utilizing HBM stacks on an interposer. The present claim 17 differs by reciting low-power double data rate (LPDDR) stacks adjacent to the base die on a substrate, and requires the compute circuitry to write back results to the host die.
It would have been obvious to a person of ordinary skill in the art to substitute the HBM stacks and interposer claimed in Kumar with LPDDR stacks and a substrate. This represents a simple substitution of one known stacked memory technology for another. A person of ordinary skill in the art would recognize that substituting HBM on an interposer with LPDDR on a substrate yields the predictable result of optimizing the system for lower power consumption and reduced manufacturing costs, while maintaining high-capacity memory access. Furthermore, configuring the compute circuitry to “write back results” is an inherent functional requirement of a compute unit executing instructions offloaded by a host processor.
Regarding dependent claims 2-8, 10-16, and 18-20: The dependent claims of the present application recite features such as parallel multipliers/adders, speculative execution, and wafer cutting techniques. These features represent known computational and manufacturing techniques in the semiconductor arts. Applying these known techniques to the base architecture claimed in Kumar would yield predictable results and does not render the claims patentably distinct.
Conclusion: Accordingly, the claims of the present application are obvious variations of the invention claimed in Kumar.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9, 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (U.S. patent application publication 20250298771 A1), hereinafter referred to as Yao, in view of Lee et al. (U.S. patent application publication 20260072855 A1), hereinafter referred to as Lee.
Claim 1: Yao teaches an integrated circuit, comprising: a host die including a plurality of processors (Yao, ¶ [0023], AI accelerator compute die such as a GPU or NPU); at least two high-bandwidth memory (HBM) stacks that communicate with the host die (Yao, ¶ [0009], one or more HBM chiplets coupled to the compute die); and compute circuitry to receive data from one or both of the HBM stacks and to execute instructions received from the host die (Yao, ¶ [0052], HBM chiplets include a mini compute die for Compute-in-Memory (CIM) localized data processing); wherein the at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row (Yao, ¶ [0030] and FIGS. 2-4, daisy-chain configuration where multiple HBM chiplets are connected in a linear sequence extending outward from the compute die). Yao does not explicitly disclose the host die and HBM stacks disposed on a base die over an interposer, nor the compute circuitry disposed on the base die between the two HBM stacks. Lee teaches an integrated circuit package comprising a base die disposed on an interposer, wherein a host device and stacked memory structures are disposed on the base die and communicate through it (Lee, ¶ [0005]-[0006], [0134]). Lee further teaches disposing active compute/interface circuitry within the base die beneath and adjacent to the memory stacks (Lee, ¶ [0212]-[0213]). Before the effective filling date of the claimed inventions, it would have been obvious to modify Yao to mount the host and daisy-chained HBM stacks on an active base die over an interposer as taught by Lee, to reduce routing latency and enable localized processing. In doing so, the compute circuitry of the base die would inherently be disposed in the physical routing space between the sequentially arranged HBM stacks to facilitate Yao’s daisy-chain data forwarding.
Claim 3: Yao teaches the compute circuitry performs localized data processing and ML computations (Yao, ¶ [0052]). It is well known in the art that compute circuitry for AI/ML accelerators inherently includes a plurality of multipliers and a plurality of adders to perform operations in parallel.
Claim 4: Yao teaches the compute circuitry is operative to write back results of executing the instructions to the host die (Yao, ¶ [0052], transferring information back to the AI accelerator after localized data processing).
Claim 5: Yao teaches the compute circuitry is operative to write back results of executing the instructions to one or both of the HBM stacks (Yao, ¶ [0057], accessing internal DRAM and updating the corresponding data).
Claim 6: Yao teaches the compute circuitry is operative to speculatively execute the instructions (Yao, ¶ [00554], execute instructions stored on a non-transitory computer-readable medium to facilitate memory access, data transfer, and request routing between interconnected memory components in a modular HBM architecture.
Claim 7: Yao teaches the compute circuitry is operative to receive one or more commands from the host die, perform operations according to the one or more commands, and send results back to the host die when the results are needed by the host die (Yao, ¶ [0052], [0055], receiving memory access requests/commands, performing CIM operations, and returning data to the compute die).
Claim 8: Yao teaches aggregating bandwidth across multiple nodes (Yao, ¶ [0007]-[0008]). Lee teaches the base die includes a controller to send outgoing data (Lee, ¶ [0068]-[0069]). It would have been obvious to configure the base die controller to send outgoing data from the two HBM stacks and the compute circuitry at a higher data rate than the data rate supported by each individual HBM stack to maximize system bandwidth.
Claim 9: Yao in view of Lee teaches a base die, comprising: at least two high-bandwidth memory (HBM) stacks disposed on the base die and communicate with a host die through the base die and an interposer; and compute circuitry on the base die to receive data from one or both of the HBM stacks and to execute instructions received from the host die, at least a portion of the compute circuitry disposed on the base die between the two HBM stacks, wherein the at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. (See the rationale set forth for Claim 1, which applies equally to the base die of Claim 9).
Claim 11: Yao teaches the compute circuitry includes a plurality of multipliers and a plurality of adders to perform operations in parallel. (See the rationale set forth for Claim 3).
Claim 12: Yao teaches the compute circuitry is operative to write back results of executing the instructions to the host die. (See the rationale set forth for Claim 4).
Claim 13: Yao teaches the compute circuitry is operative to write back results of executing the instructions to one or both of the HBM stacks. (See the rationale set forth for Claim 5).
Claim 14: Yao teaches the compute circuitry is operative to speculatively execute the instructions (Yao, ¶ [00554], execute instructions stored on a non-transitory computer-readable medium to facilitate memory access, data transfer, and request routing between interconnected memory components in a modular HBM architecture.
Claim 15: Yao teaches the compute circuitry is operative to receive one or more commands from the host die, perform operations, and send results back to the host die. (See the rationale set forth for Claim 7).
Claim 16: Yao in view of Lee teaches a controller to send outgoing data from the two HBM stacks and the compute circuitry at a higher data rate than the data rate supported by each HBM stack. (See the rationale set forth for Claim 8).
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (U.S. patent application publication 20250298771 A1), hereinafter referred to as Yao, in view of Lee et al. (U.S. patent application publication 20260072855 A1), hereinafter referred to as Lee and further in view of Enquist (U.S. patent application publication 20190355706 A1).
As for claims 2 and 10, as set forth in the rejection of independent claims 1 and 9 above, Yao in view of Lee teaches the claimed integrated circuit and base die architecture, including at least two HBM stacks communicating with a host die, wherein the HBM stacks are arranged in a row with the host die at one end.
Yao and Lee do not explicitly disclose that the at least two HBM stacks are fabricated on a wafer containing a plurality of HBM stacks arranged in rows and columns, and wherein the wafer is cut between every row and between every other column to create a plurality of pairs of HBM stacks.
Enquist teaches methods for fabricating and packaging stacked devices, including High Bandwidth Memory (HBM) dies, using wafer-level packaging (WLP) (Enquist, ¶ [0054], variegated dies can be logic dies, image sensor dies, high bandwidth memory (HBM) dies). Enquist teaches that integrated circuit dies are fabricated on semiconductor wafers (which inherently comprise a plurality of circuits arranged in rows and columns) and subsequently diced (cut) from the wafer to yield chips of specific footprint sizes and form factors for subsequent 3D stacking and direct-bonding (Enquist, ¶ [0002], packaging technologies dice wafers into individual integrated circuit microchips; ¶ [0023], as the area of wafer surface increases, the number of semiconductor dies obtainable from a wafer also increases).
Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the wafer dicing process taught by Enquist to cut between every row and between every other column to create a plurality of pairs of HBM stacks for use in the combined Yao/Lee architecture.
Motivation to Combine/Modify: A person of ordinary skill in the art would have been motivated to adjust the dicing streets (cutting every other column) of the HBM wafers taught by Enquist to intentionally yield pre-joined pairs of HBM stacks. Yao explicitly teaches a modular memory architecture that utilizes a 2-node daisy-chain configuration (Yao, FIG. 2 and ¶ [0034], high-end AI accelerator with two nodes in the daisy-chain). By cutting the wafer to yield pairs of HBM stacks rather than individual, singulated dies, the manufacturer inherently preserves the ultra-high-density native silicon interconnects between the two adjacent HBM stacks. This modification predictably eliminates the need to physically align and bond two separate HBM chiplets together downstream, thereby increasing production yield, reducing packaging complexity, and perfectly accommodating the 2-node daisy-chain topology desired by Yao, which aligns with Enquist’s stated goals of achieving highly efficient, high-yield wafer-level packaging (Enquist, ¶ [0020]-[0021]).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (U.S. patent application publication 20250298771 A1), hereinafter referred to as Yao, in view of Lee et al. (U.S. patent application publication 20220066655), hereinafter referred to as Lee2.
Regarding Claim 17, Yao teaches an integrated circuit, comprising:
A host die disposed on a substrate and including a plurality of processors (Yao, ¶ [0023], AI accelerator compute die such as a GPU or NPU integrated within a System-in-Package (SiP) arrangement);
A base die disposed on the substrate (Yao, ¶ [0052], teaching a “mini compute die” integrated into the memory chiplet nodes on the SiP substrate);
At least two memory stacks adjacent to the base die and communicating with the host die through the base die (Yao, ¶ [0030], [0052], multiple memory chiplets arranged in a daisy-chain or grid, communicating with the host/compute die through the local mini compute die nodes); and
Compute circuitry on the base die operative to receive data from one or both of the memory stacks, execute instructions received from the host die, and write back results of executing the instructions to the host die (Yao, ¶ [0052], teaching Compute-in-Memory (CIM) capabilities where the mini compute die performs localized data processing/computations on the memory data before transferring the information back to the AI accelerator host).
Yao does not explicitly disclose the host die and HBM stacks disposed on a base die over an interposer, nor the compute circuitry disposed on the base die between the two HBM stacks. Lee teaches an integrated circuit package comprising a base die disposed on an interposer, wherein a host device and stacked memory structures are disposed on the base die and communicate through it (Lee, ¶ [0005]-[0006], [0134]). Lee further teaches disposing active compute/interface circuitry within the base die beneath and adjacent to the memory stacks (Lee, ¶ [0212]-[0213]). Before the effective filling date of the claimed inventions, it would have been obvious to modify Yao to mount the host and daisy-chained HBM stacks on an active base die over an interposer as taught by Lee, to reduce routing latency and enable localized processing. In doing so, the compute circuitry of the base die would inherently be disposed in the physical routing space between the sequentially arranged HBM stacks to facilitate Yao’s daisy-chain data forwarding.
Yao teaches the use of High-Bandwidth Memory (HBM) stacks, but does not explicitly disclose that the memory stacks are low-power double data rate (LPDDR) stacks.
Lee2 teaches memory systems utilizing low-power double data rate (LPDDR) synchronous DRAM (SDRAM) stacks to provide high-speed data access while significantly reducing energy consumption (Lee, ¶ [0014], teaching that LPDDR memory uses less power than other types of DDR SDRAM, extends battery life in mobile devices, and reduces electricity usage and operational costs across large data centers).
Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the integrated circuit architecture of Yao by substituting the HBM stacks with the LPDDR stacks taught by Lee.
Motivation to Combine: A person of ordinary skill in the art would have been motivated to substitute Yao’s HBM memory with the LPDDR memory of Lee because Lee explicitly teaches that LPDDR provides critical power-saving benefits for both mobile devices and server applications (Lee, ¶ [0014]). Yao teaches that its modular memory architecture is designed to be highly adaptable to varying system requirements, explicitly noting that excessive bandwidth in certain systems “could result in unnecessary power consumption and cost” (Yao, ¶ [0029]). Therefore, substituting HBM with LPDDR is a simple substitution of one known memory standard for another to yield the predictable result of a highly scalable, Compute-in-Memory (CIM) architecture (Yao’s benefit) that operates with significantly reduced power consumption and improved thermal/energy efficiency (Lee’s benefit).
As for claim 18, Yao teaches the compute circuitry performs localized data processing and ML computations (Yao, ¶ [0052]). It is well known in the art that compute circuitry for AI/ML accelerators inherently includes a plurality of multipliers and a plurality of adders to perform operations in parallel.
As for claim 19, (Yao, ¶ [0057], accessing internal DRAM and updating the corresponding data). Yao does not teach the compute circuitry is operative to write back results of executing the instructions to one or both of the LPDDR stacks. However, with Lee2 LPDDR substitution as rejected in claim 17. Therefore, substituting HBM with LPDDR is a simple substitution of one known memory standard for another to yield the predictable result of a highly scalable, Compute-in-Memory (CIM) architecture (Yao’s benefit) that operates with significantly reduced power consumption and improved thermal/energy efficiency (Lee’s benefit).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (U.S. patent application publication 20250298771 A1), hereinafter referred to as Yao, in view of Lee et al. (U.S. patent application publication 20260072855 A1), hereinafter referred to as Lee and further in view of Lee et al. (U.S. patent application publication 20220066655), hereinafter referred to as Lee2.
As for claim 20, Yao and Lee do not teach the base die includes a LPDDR controller to send outgoing data from the two LPDDR stacks and the compute circuitry at a higher data rate than the data rate supported by each LPDDR stack. Yao teaches aggregating bandwidth across multiple nodes (Yao, ¶ [0007]-[0008]). Lee teaches the base die includes a controller to send outgoing data (Lee, ¶ [0068]-[0069]). It would have been obvious to configure the base die controller to send outgoing data from the two HBM stacks and the compute circuitry at a higher data rate than the data rate supported by each individual HBM stack to maximize system bandwidth. Further, with Lee2 LPDDR substitutions. Therefore, substituting HBM with LPDDR is a simple substitution of one known memory standard for another to yield the predictable result of a highly scalable, Compute-in-Memory (CIM) architecture (Yao’s benefit) that operates with significantly reduced power consumption and improved thermal/energy efficiency (Lee’s benefit).
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim 20260068174 - How it is related: Lim operates in the same advanced packaging space, discussing multi-die assemblies that include a base die, a host die (CPU/SOC), and HBM stacks. It also shares the general goal of reducing data latency and improving memory bandwidth.
Why it is not applicable: Lim’s structural architecture is fundamentally different from your claimed invention and cannot be used for a rejection against claims 1, 9, and 17 for the following reasons:
Missing Compute Circuitry on the Base Die: In Lim, the base die (102) acts merely as a routing interposer or spacer. The compute logic is located entirely in the top IC die. Lim does not teach placing active compute circuitry on the base die itself to execute instructions offloaded by the host.
Tong (2023/0387032)
Core Focus: Ultrafine line/space (L/S) laminate substrates with embedded high-thermal-conductivity cores for advanced packaging.
Summary: This Tong reference addresses the thermal management, Coefficient of Thermal Expansion (CTE) mismatch, and wiring density challenges associated with packaging high-power processors and memory. Tong’s solution is a hybrid substrate architecture that combines standard panel-level build-up layers with wafer-level, ultrafine pitch redistribution layers (RDLs). To handle the massive heat generated by advanced chips, Tong teaches embedding a low-CTE, high-thermal-conductivity core (such as a Cu-Invar-Cu clad metal block) inside the substrate. It also discusses embedding components like voltage regulators or passive silicon bridges into this core.
How it is related: This reference operates in the exact same 2.5D/3D advanced packaging environment as your invention. It explicitly discusses mounting processors (CPUs/GPUs) and High-Bandwidth Memory (HBM) stacks side-by-side on an interposer or advanced laminate substrate (see FIG. 8 and paragraph [0097]).
Tong lacks the structural compute-near-memory limitations and the specific linear die arrangement required by claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tim Vo whose telephone number is (571)272-3642. The examiner can normally be reached on Monday-Thursday 5:30 AM – 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571)272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/www.uspto.gov/interviewpractice.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIM T VO/
Supervisory Patent Examiner, Art Unit 2138
Prosecution Insights