DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 15, 16, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su (US 20240029603 A1).
Regarding claim 1, Su teaches a state self-test method for a driver chip, applied to the driver chip comprising first-type registers, the state self-test method comprising:
performing initialization of the first-type registers based on a received initialization instruction, and receiving and storing an auxiliary check value (Fig. 3C, [0073], where in step S210 the driving counter UC is zeroed and where the start signal ST is received);
calculating a checked value based on a received state self-test instruction and actual register values of the first-type registers (Figs. 3C and 3D, [0073]-[0074], where the driving counter is calculated as initiated by the instruction; [0074], [0079], where the counter is an incremented register value); and
determining whether an operating state of the driver chip is abnormal by determining whether a relationship between the checked value and the auxiliary check value meets a preset condition (Fig. 3C, [0076], where the driver is mark as abnormal where the proper number of tests fails to be executed, i.e., where the counter does not increment to N for testing up to the Nth driver).
Regarding claim 2, Su teaches the state self-test method for a driver chip according to claim 1, wherein the auxiliary check value is related to target register values of the first-type registers after the initialization ([0076], where the check value is the number of driver chips N to be checked such that the target register value after being zeroed would be N).
Regarding claim 15, Su teaches the state self-test method for a driver chip according to claim 1, wherein after the determining whether an operating state of the driver chip is abnormal by determining whether a relationship between the checked value and the auxiliary check value meets a preset condition, the state self-test method further comprises:
reporting, upon determining that the operating state of the driver chip is abnormal, an abnormal operating state based on a received self-test state query request or reporting the abnormal operating state actively ([0076], where an abnormal operation signal is generated for notifying).
Regarding claim 16, Su teaches a state self-test method for a driver chip, applied to a timing controller, the state self-test method comprising:
sending an initialization instruction to the driver chip, the initialization instruction comprising target register values of first-type registers in the driver chip, determining an auxiliary check value based on the target register values, and sending the auxiliary check value to the driver chip (Figs. 3C and 3D, [0073]-[0074], where the driving counter is calculated as initiated by the instruction; [0074], [0079], where the counter is an incremented register value);
sending a state self-test instruction to the driver chip (Figs 3C and 3D, [0073], where the self-test begins after S200); and
receiving an operating state reported by the driver chip (Fig. 3C, [0076], where the driver is mark as abnormal where the proper number of tests fails to be executed, i.e., where the counter does not increment to N for testing up to the Nth driver).
Regarding claim 18, Su teaches a driver chip, comprising first-type registers, a storage module, a calculation module, and a determination module (Figs. 3C and 3D, [0073]-[0076], where there are elements for storing, incrementing, and determining an outcome based on calculated values),
wherein the calculation module is electrically connected to the first-type registers and the determination module, and is configured to calculate a checked value based on actual register values of the first-type registers; the storage module is configured to store an auxiliary check value (Figs. 3C and 3D, [0073]-[0074], where the driving counter is calculated as initiated by the instruction; [0074], [0079], where the counter is an incremented register value); and the determination module is electrically connected to the storage module, and is configured to determine whether an operating state of the driver chip is abnormal by determining whether a relationship between the auxiliary check value and the checked value meets a preset condition (Fig. 3C, [0076], where the driver is mark as abnormal where the proper number of tests fails to be executed, i.e., where the counter does not increment to N for testing up to the Nth driver).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Su (US 20240029603 A1) in view of Mukherjee et al. (US 20170205462 A1, hereafter Mukherjee).
Regarding claim 8, Su teaches the state self-test method for a driver chip according to claim 2, wherein receiving and storing an auxiliary check value comprises: performing the initialization of the first-type registers based on the received initialization instruction, and receiving the auxiliary check value and story the auxiliary check value (Fig. 3C, [0073], where in step S210 the driving counter UC is zeroed and where the start signal ST is received).
But, Su does not teach the method wherein the driver chip further comprises second-type registers, wherein the auxiliary value check is stored in the second-type registers. However, this was well known in the art as evidenced by Mukherjee (Fig. 4, [0034], where there are different registers 420 and 430 for storing data to be compared, the expected data register 420 receiving data from storage 120 to be compared to received data register 430 having test response data). Su teaches a method of operation for a display driver self-test. Mukherjee teaches a built-in self-test method (BIST) that is generally applicable to integrated circuits ([0004]-[0005]). While Su necessarily teaches storage or registers for holding data, it is silent with respect to whether or not this storage would include “second-type registers” different than “first-type registers” reasonably interpreted as the memory in Su. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the self-test method of Su to incorporate circuitry from Mukherjee and that such an implementation would have yielded a predictable result.
Allowable Subject Matter
Claims 3-7, 9-14, 17, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The feature, as found in claims 3, 4, 6, 9, and 19 of a method “wherein the auxiliary check value is related to a sum of the target register values of the first-type registers (Fig. 3)” is not found along with the rest of the limitations of claims 3, 4, 6, 9 and 19.
The feature, as found in claims 10, 11, 14, and 17, of a method “wherein at least one of the second-type registers comprises a reset flag bit; and prior to the performing initialization of the first-type registers based on a received initialization instruction, and receiving and storing an auxiliary check value, the state self-test method further comprises: receiving a reset instruction, and writing a reset flag bit value included in the reset instruction into the reset flag bit; and resetting the second-type registers when the reset flag bit value of the reset flag bit is valid (Fig. 5)” or “wherein at least one of the second-type registers further comprises a self-test result flag bit; and the determining whether an operating state of the driver chip is abnormal by determining whether a relationship between the checked value and the auxiliary check value meets a preset condition comprises: determining the operating state of the driver chip by determining whether the relationship between the checked value and the auxiliary check value meets the preset condition, and storing a first numerical value in the self-test result flag bit when the operating state of the driver chip is abnormal (Fig. 5)” is not found in the prior art along with the rest of the limitations of claims 10, 11, 14, and 17.
The feature, as found in claims 13 and 17, of a method “wherein the state self- test instruction further comprises self-test interval time data; and the calculating a checked value based on a received state self-test instruction and actual register values of the first-type registers comprises: obtaining a self-test interval time based on the self-test interval time data in the state self-test instruction, and calculating the checked value based on the actual register values of the first-type registers every self-test interval time; and wherein the driver chip further comprises second-type registers, wherein the self-test interval time is stored in the second-type registers; the second-type registers comprise a third register, wherein the third register comprises a self-test interval time data bit, and the self-test interval time data is stored in the self-test interval time data bit; and the third register further comprises at least one second check data bit, wherein a second check data value of the second check data bit is related to a self-test interval time data value of the self-test interval time data bit (Fig. 7)” is not found in the prior art along with the rest of the limitations of claims 13 and 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER D MCLOONE whose telephone number is (571)272-4631. The examiner can normally be reached M-F 9 AM - 5 PM.
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/PETER D MCLOONE/Primary Examiner, Art Unit 2621