DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 17 are objected to because of the following informalities: “and allocate the second portion to the external after the event is detected, without storing the external data in the first portion”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12,340,116. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following analysis:
Instant application 19/218,377.
U.S. Patent 12,340,116.
1. A memory controller comprising: a processor configured to detect an event; an arbiter configured to allocate a buffer memory including a first portion and a second portion; wherein the arbiter is configured to allocate the first portion to external data before the event is detected, without storing the external data in the second portion, and allocate the second portion to the external after the event is detected, without storing the external data in the first portion.
2. The memory controller of The memory controller of the external data is associated with a read request or a write request from an external device.
1. A memory system comprising: a storage device; a buffer memory including a first portion and a second portion; and a memory controller suitable for: detecting a set event, storing external data in the first portion before the event is detected, without storing the external data in the second portion, and storing the external data in the second portion after the event is detected, without storing the external data in the first portion, wherein the external data is associated with a read request or a write request from an external device.
3. The memory controller of claim 1, wherein the first portion has a bandwidth greater than that of the second portion.
2. The memory system of claim 1, wherein the first portion has a bandwidth greater than that of the second portion.
4. The memory controller of claim 1, wherein the first portion is arranged inside the memory controller; and the second portion is arranged outside the memory controller.
3. The memory system of claim 1, wherein the first portion is arranged inside the memory controller.
4. The memory controller of claim 1, wherein the first portion is arranged inside the memory controller; and the second portion is arranged outside the memory controller.
4. The memory system of claim 1, wherein the second portion is arranged outside the memory controller.
5. The memory controller of claim 1, wherein the arbiter is configured to allocate the first portion to internal data.
6. The memory controller of claim 5, wherein the memory controller is configured to control a storage device, and the internal data is transferred between the memory controller and the storage device regardless of the read request or the write request from an external device.
5. The memory system of claim 1, wherein the memory controller stores internal data in the first portion, wherein the internal data is transferred between the memory controller and the storage device regardless of the read request or the write request.
7. The memory controller of claim 5, wherein the memory controller is configured to control a storage device, and the internal data comprises data associated with a background operation performed on the storage device.
6. The memory system of claim 5, wherein the internal data comprises data associated with a background operation performed on the storage device.
8. The memory controller of claim 1, wherein the memory controller is configured to control a storage device, and the event is triggered based on an available space capacity of the storage device.
7. The memory system of claim 1, wherein the event is triggered based on an available space capacity of the storage device.
9. The memory controller of claim 1, wherein the memory controller is configured to control a storage device, and the event is triggered when a background operation performed on the storage device is activated.2
8. The memory system of claim 1, wherein the event is triggered when a background operation performed on the storage device is activated.
10. A memory controller comprising: a processor configured to monitor an event is being triggered; an arbiter configured to store external data to a second portion of a buffer memory without storing the external data in a first portion of the buffer memory when a condition to trigger the event is satisfied, and to store external data to the first portion without storing the external data in the second portion when the condition is not satisfied.
9. A memory controller comprising: a first memory device; a second memory device; and a processor suitable for: detecting an event, which is triggered by at least one of an available space capacity of a storage device and an aging detection signal of the storage device, before the event is detected, storing, in the first memory device, without storing in the second memory device, external data read-requested or write-requested by an external device, and after the event is detected, storing, in the first memory devices, without storing in the second memory device, internal data, which is transferred regardless of the read request or the write request from the external device.
11. The memory controller of The memory controller of the external data is associated with a read request or a write request from an external device.
10. The memory controller of claim 9, wherein the processor stores the external data in the second memory device after the event is detected.
12. The memory controller of claim 10, wherein the first portion has a bandwidth greater than that of the second portion.
11. The memory controller of claim 10, wherein the first memory device has a bandwidth greater than that of the second memory device.
13. The memory controller of claim 10, wherein the first portion is arranged inside the memory controller; and the second portion is arranged outside the memory controller.
12. The memory controller of claim 10, wherein the first memory device is arranged inside the memory controller.
16. The memory controller of The memory controller of wherein the memory controller is configured to control a storage device, and the event is triggered when a background operation performed on the storage device is activated.
14. The memory controller of claim 10, wherein the arbiter is configured to allocate the first portion to internal data.
15. The memory controller of claim 10, wherein the memory controller is configured to control a storage device, and the event is triggered based on an available space capacity of the storage device.
13. The memory controller of claim 9, wherein the processor activates the aging detection signal when a background operation with respect to the storage device is required.
17. A memory system comprising: a storage device; a first memory device; a second memory device; a processor configured to detect an event associated with the storage device; and an arbiter configured to allocate the first memory device to external data before the event is detected, without storing the external data in the second memory device, and allocate the second memory device to the external after the event is detected, without storing the external data in the first memory device.
14. A method of operating a memory system which includes a storage device and a memory controller controlling a buffer memory including a first portion and a second portion, the method comprising: detecting, by the memory controller, a set event; before the event is detected, storing, by the memory controller, in the first portion, external data, which is associated with a read request or a write request from an external device, without storing the external data in the second portion; and after the event is detected, storing, by the memory controller, the external data in the second portion without storing the external data in the first portion.
19. The memory system of claim 17, wherein the arbiter is configured to allocate the first portion to internal data.
15. The method of claim 14, further comprising: after the event is detected, storing, by the memory controller, in the first portion, internal data, which are transferred between the memory controller and the storage device regardless of the read request or the write request.
17. The method of claim 14, wherein the event is triggered based on an available space capacity of the storage device.
20. The memory system of claim 17, wherein the event is triggered based on an available space capacity of the storage device or when a background operation performed on the storage device is activated
17. The method of claim 14, wherein the event is triggered based on an available space capacity of the storage device.
18. The method of claim 14, wherein the event is triggered when a background operation performed on the storage device is activated.
18. The memory system of claim 17, wherein the first memory device has a bandwidth greater than that of the second memory device.
19. The method of claim 14, wherein the first portion has a bandwidth greater than that of the second portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gupta discloses a data storage system operations in a first mode, portions of cached write data not yet destaged to a data storage device are copied from the cache to a first area in a flash-based memory. In response to a vault operation event, the data storage system operates in a second mode in which all remaining portions of cached write data from the cache not currently included in the first area are copied to a second area of the flash-based memory.
Flynn discloses a cache memory comprises a first cache and a second cache, each caches data corresponds to a portion of a shared logical address space.
Muthiah discloses a memory device comprises a first buffer stores data from an SLC block, and re-write the data to the same or different memory block as a first portion of a garbage collection process, and a second buffer stores data from a MLC block and re-write the data to the same or different memory block as a second portion of the garbage collection process.
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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