Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-3 and 5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2: The claim recites that data is copied from the embedded host memory to the user space memory using cyclic DMA.
Issue: This contradicts the specification. Paragraphs [0049] and [0060] explicitly state that the cyclic DMA technique is used to write data from the firmware to the host memory. The specification states that the driver code (software) copies the data from the host memory to the user space (Paragraph [0046]). DMA is not used for the host-to-user-space transfer.
Claim 3: The claim recites that the “writing and copying of the DFOS data into the user space memory is controlled by a valid bit…”
Issue: Paragraph [0049] states that the firmware uses the valid bit when writing data to the host memory to notify the driver. The valid bit does not control the writing into the user space memory; it controls the firmware-to-driver handoff in the host memory.
Claim 5: The claim recites “the user space memory to which the firmware writes the DFOS data…”
Issue: This is a fatal contradiction of the specification. Paragraph [0045] explicitly states that the firmware writes data “into the embedded host memory directly.” The firmware does not write to the user space memory; the kernel driver handles that transfer (Paragraph [0046]).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 (Grammar/Punctuation): The claim contains errant commas that make the limitations confusing to read (e.g., “copying, the DFOS data”, “requesting, by a first dedicated user space thread, the DFOS data”).
Claim 1 (Logical Flow): The claim recites “requesting… the DFOS data copied to the user space memory”. This implies the thread is requesting data that has already been copied to the user space memory. However, Paragraph [0078] of the specification states that the data reading thread requests the kernel driver to read data into the buffer (i.e., it requests the data from the driver, not data already in the user space).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1 is directed to a statutory category because it claims a method (process). However, the claim is directed to an abstract idea and does not recite significantly more.
Step 2A, Prong 1: The claim recites a judicial exception. The claim recites the steps of “writing DFOS data,” “copying… the DFOS data,” “requesting… the DFOS data,” and “sending… the DFOS data.” These limitations recite the abstract idea of collecting, storing, and transmitting information. Under the USPTO eligibility guidelines, the collection, storage, and transmission of data is considered an abstract idea that falls within the enumerated groupings of mental processes (because the steps of receiving, copying, and sending information can practically be performed in the human mind or with a pen and paper) and certain methods of organizing human activity (managing the flow of data).
Step 2A, Prong 2: The claim does not integrate the judicial exception into a practical application. Because the claim recites an abstract idea, the claim must be evaluated to determine if the abstract idea is integrated into a practical application. The additional elements recited in the claim are an “embedded host memory,” a “user space memory,” a “first dedicated user space thread,” a “second dedicated user space thread,” and a “remote system.”
These additional elements merely recite generic computer components and programming constructs used to apply the abstract idea. While the specification describes an improvement to embedded system technology (overcoming software and network jitter by using a cyclic DMA technique and a single valid bit for firmware-to-driver signaling), Claim 1 does not recite these specific technical features. Instead, Claim 1 recites data transfer at a high level of generality. The generic memory and threads do not effect an improvement to the functioning of the computer itself, nor do they apply the abstract idea in a meaningful way beyond generally linking the use of the abstract idea to a generic technological environment. Therefore, the claim does not integrate the abstract idea into a practical application.
Step 2B: The claim does not recite significantly more than the abstract idea. Because the claim is directed to an abstract idea that is not integrated into a practical application, the claim must be evaluated to determine if it recites significantly more than the abstract idea itself.
The additional elements (host memory, user space memory, user space threads, and a remote system), when considered individually and as an ordered combination, amount to no more than well-understood, routine, and conventional computer components engaged in basic data processing. Utilizing memory to store data and utilizing threads to request and send data are standard, conventional programming techniques. They do not add a specific limitation other than what is well-understood, routine, and conventional in the field.
Therefore, the claim does not amount to significantly more than the abstract idea itself and is ineligible subject matter.
Claims 2-5 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Step 2A, Prong 1: The claims recite a judicial exception. Claims 2-5 depend from Claim 1. As established in the rejection of Claim 1, the base method is directed to the abstract idea of collecting, storing, and transmitting data (a mental process and/or method of organizing human activity). Claims 2-5 incorporate this abstract idea.
Step 2A, Prong 2: The claims do not integrate the judicial exception into a practical application. Claims 2-5 recite additional elements, including a “cyclic Direct Memory Access (cyclic DMA) technique” (Claim 2), a “valid bit that is set by firmware and cleared by software” (Claim 3), firmware operating at a “register-transfer level” (Claim 4), and a user space memory configured as a “buffer, divided into multiple frames” using the valid bit for “valid status and a full status” (Claim 5).
Under USPTO guidelines, an abstract idea can be integrated into a practical application if the additional elements effect a specific improvement to the functioning of a computer or technological process. However, the additional elements in Claims 2-5 are claimed in a manner that is technically contradictory to the specification and functionally inoperable as written.
Specifically:
Claim 2 recites using cyclic DMA to copy data from the embedded host memory to the user space memory.
Claim 3 recites that the valid bit controls writing into the user space memory.
Claim 5 recites that the firmware writes to the user space memory.
The specification explicitly states that the firmware uses cyclic DMA to write to the embedded host memory, not the user space memory (Paragraphs [0045], [0049]). The transfer to the user space memory is performed by kernel driver software, not by cyclic DMA or firmware. Because the claims recite a sequence of operations and a hardware/software architecture that contradicts the specification and is technically nonsensical as arranged, these limitations cannot be credited as providing a specific, operable improvement to the functioning of the computer. An inoperable or contradictory arrangement of computer components does not integrate the abstract idea into a practical application.
Step 2B: The claims do not recite significantly more than the abstract idea. Because the claims do not integrate the abstract idea into a practical application, they must be evaluated to determine if they recite significantly more than the abstract idea itself.
While cyclic DMA, valid bits, and memory buffers are specific technical tools, their misapplication in the current claim language fails to provide an inventive concept. Reciting technical jargon in an arrangement that does not actually solve the stated problem (because the claimed data flow contradicts the actual technical solution described in the specification) amounts to no more than adding insignificant, extra-solution activity to the abstract idea. Therefore, Claims 2-5 do not amount to significantly more than the abstract idea itself and are ineligible subject matter.
Examiner’s Note: The Examiner recognizes that the specification (e.g., Paragraphs [0045]-[0053]) describes a genuine technical improvement to embedded system throughput by using cyclic DMA to write from firmware to host memory, and using a valid bit to synchronize with a kernel driver. If Applicant amends the claims to accurately reflect this specific architectural flow as described in the specification—thereby curing the § 112(a) and § 112(b) issues—the claims would likely integrate the abstract idea into a practical application and overcome this § 101 rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable over Campos (US 1189900) in view of Jeffrey (11886343).
Regarding Claim 1: Campos teaches a computer-implemented method for transferring data from a distributed fiber optic sensing (DFOS) system to a remote system, comprising:
A distributed fiber optic sensing (DFOS) system: Campos teaches a DFOS system 112 that generates and collects sensing data (Campos, Abstract; Paragraph [0036]).
Sending the DFOS data to a remote system: Campos teaches that the controlling and/or processing components of the DFOS system can be implemented in a remote data center or in a distributed computing system, such as a cloud computing system (Campos, Paragraph [0041]).
Campos does not explicitly detail the internal software memory management steps of writing to an embedded host memory, copying to a user space memory, and using a first dedicated user space thread to request data and a second dedicated user space thread to send the data.
However, Jeffrey teaches specific internal memory and threading architecture for high-speed data transfer. Jeffrey teaches writing data to a memory buffer using a multi-threaded architecture comprising a producer computing thread (which writes/requests data into the buffer) and a consumer computing thread (which reads/sends the data out of the buffer) (Jeffrey, Paragraphs [0001]-[0003], [0041]). Jeffrey operates in a standard operating system environment (e.g., CPU to GPU communication) which inherently utilizes host memory and user space memory for thread execution (Jeffrey, Paragraph [0002]).
Motivation to Combine (Campos and Jeffrey): Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art at the time of the invention to implement the multi-threaded producer/consumer memory architecture of Jeffrey into the DFOS system of Campos. The motivation, as explicitly stated in Jeffrey, is to eliminate the need for software locks (mutexes), thereby reducing thread stalls, preventing high-priority threads from being blocked, and vastly improving the speed and throughput of data transfers (Jeffrey, Paragraphs [0002], [0032]-[0034]). Implementing this in Campos would allow the DFOS system to efficiently stream massive amounts of real-time sensing data to the remote cloud system without software bottlenecks.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Campos (US 1189900) in view of Jeffrey (11886343), and further in view of Spilo (6182165).
Regarding Claim 2: Campos and Jeffrey do not explicitly detail using a cyclic Direct Memory Access (DMA) technique. However, Spilo teaches transferring data directly to memory using a buffer descriptor ring DMA controller (which is structurally and functionally identical to a cyclic DMA) to transfer data from a circular buffer in memory (Spilo, Paragraph [0008]). Motivation to Combine: It would have been obvious to a person of ordinary skill in the art to integrate the cyclic/ring DMA of Spilo into the embedded system of Campos and Jeffrey. The motivation, as stated in Spilo, is to allow direct memory access with “minimal processor intervention,” thereby reducing interrupt latency and bandwidth consumption during high-speed data communications (Spilo, Paragraphs [0007], [0011]).
Regarding Claim 3: Campos and Jeffrey do not explicitly detail a valid bit that is set by firmware and cleared by software. However, Spilo teaches this limitation. Spilo discloses an ownership flag (OWN 256) within the buffer descriptor. The hardware/DMA unit sets the flag to relinquish control (indicating the data is valid/ready), and the software clears the flag after processing the buffer (Spilo, Paragraphs [0010], [0026]).
Regarding Claim 4: Campos and Jeffrey do not explicitly detail firmware operating at a register-transfer level (RTL). However, Spilo teaches that the DMA controller and microcontroller are implemented on a monolithic semiconductor substrate (hardware/RTL) executing embedded logic/firmware to handle the data transfers independently of the main execution unit (Spilo, Paragraphs [0005], [0014]).
Regarding Claim 5: Campos and Jeffrey do not explicitly detail the buffer being divided into multiple frames, where the valid bit indicates both valid status and full status. However, Spilo teaches that the buffer descriptor ring is divided into multiple individual buffers (frames) (Spilo, FIG. 3, buffers 206a-c). Furthermore, Spilo teaches that the ownership flag (valid bit) indicates whether the buffer is valid/ready for the DMA or software to process, which inherently acts as a full/empty status indicator to prevent the system from overlapping or overflowing the buffers (Spilo, Paragraphs [0010], [0023]-[0024]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tim Vo whose telephone number is (571)272-3642. The examiner can normally be reached on Monday-Thursday 5:30 AM – 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571)272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
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/TIM T VO/Supervisory Patent Examiner, Art Unit 2138
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