DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitations "an inductor…a capacitor…an additional capacitor…an additional switching element" in lines 2-4. The limitations have been previously introduced with relation to the first bandpass filter in claim 2. For the sake of clarity, the limitations introduced should be rewritten to differentiate between the limitations introduced in claim 2, of which claim 4 ultimately depends upon. For examination purposes, examiner has interpreted “an inductor…a capacitor…an additional capacitor…an additional switching element” to read “a second inductor…a second capacitor…a second additional capacitor…a second additional switching element”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chung et al. (“A 10–40 GHz frequency quadrupler source with switchable bandpass filters and > 30 dBc harmonic rejection”, IEEE Radio Frequency Integrated Circuits Symposium, Honolulu, HI, USA, 2017, pp. 49-52), hereinafter Chung.
Regarding claim 1, Chung discloses, in figure 2 & 3, a high spectral purity frequency quadrupler employing a bandpass filter, the frequency quadrupler comprising a first push-pull doubler that doubles a frequency of an input ultra-high frequency signal (section II, para. 3, “4 GHz signal is applied into the first doubler…the output frequency range of the first-stage doubler is 8-13 GHz”), a first bandpass filter that passes a signal having a frequency band twice that of the input ultra-high frequency signal among output signals of the first push-pull doubler (first bandpass filter coupled to the output of the first doubler passes the signal in the frequency band twice that of the input signal, see figure 2, P1), a second push-pull doubler that doubles an ultra-high frequency signal passing through the first bandpass filter (second doubler stage doubles the frequency signal passing through the first bandpass filter), and a second bandpass filter that passes a signal having a frequency band twice that of the signal passing through the first bandpass filter among output signals of the second push-pull doubler (section II, para. 3, “for this second [bandpass] filter, the 1-bit tuning narrows the…passband of 16-26 GHz to a passband of 16-20 GHz for a 4 GHz input”,
wherein the first push-pull doubler comprises a first input impedance matching unit (1pF capacitor, balun, 150 Ohm resistor, 350fF capacitor, and center tap of the balun form the first input impedance matching unit, see figure 3), a first amplifier unit (Q1, Q2, and Q3 form the first amplifier unit), and a first output impedance matching unit (output balun and three 100fF capacitors coupled to OUT form the output impedance matching unit, see figure 3), and
wherein the first input impedance matching unit selectively transmits a second harmonic of the input ultra-high frequency signal to the first amplifier unit (section III, para. 1, “the first-stage doubler results in a 2f.sub.o conversion gain of 3-5 dB at 4-6.5 GHz for an input power of 0dBm”), and the first amplifier unit amplifies the second harmonic of the input ultra-high frequency signal to output the amplified second harmonic through the first output impedance matching unit (the first stage doubler passes through and amplifies the second harmonic of the input signal that is output to the first bandpass filter).
Regarding claim 2, Chung discloses the frequency quadrupler of claim 1, and continues to disclose, in figure 4, wherein the first bandpass filter (depicted by figure 4) is configured by connecting an inductor and a capacitor in parallel (top inductor and 290 fF capacitor connected in parallel), and an additional capacitor and an additional switching element are connected in parallel to the capacitor (top transistor with connected capacitor are connected in parallel to the 290fF capacitor), and when the additional switching element is turned off (section III, para. 2, “when the CMOS switches are OFF”), a higher frequency band signal passes therethrough than when the additional switching element is turned on (section III, para. 2, “when the CMOS switches are OFF (operation in the high band-edge)”…increased passband from 8-10.5 GHz to 8-13 GHz).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Stärke et al. (“Frequency Multiplier-by-4 (Quadrupler) with 52 dB Spurious-Free Dynamic Range for 152 GHz to 220 GHz (G-Band) in 130 nm SiGe”, IEEE Radio Frequency Integrated Circuits Symposium, Los Angeles, CA, USA, 2020, pp. 251-254), hereinafter Starke.
Regarding claim 3, Chung discloses the frequency quadrupler of claim 2, but fails to disclose wherein the second push-pull doubler comprises a second input impedance matching unit, a second amplifier unit, and a second output impedance matching unit, and
wherein the second input impedance matching unit selectively transmits a second harmonic of a signal passing through the first bandpass filter to the second amplifier unit, and the second amplifier unit amplifies the second harmonic of the signal passing through the first bandpass filter to output the amplified second harmonic through the second output impedance matching unit.
However, Starke discloses, in figure 1 & 2, wherein the second push-pull doubler (second doubler of figure 1) comprises a second input impedance matching unit (broadband balun coupled to the input In), a second amplifier unit (comprised of two lower transistors and two upper transistors, see figure 2), and a second output impedance matching unit (broadband balun coupled to the output Out), and
wherein the second input impedance matching unit selectively transmits a second harmonic of a signal passing through the first bandpass filter to the second amplifier unit (section II, para. 3, “provides rejection of the odd harmonics (including the fundamental) and gain for the even ones…simplified schematic of the doublers is given in Fig. 2. They are implemented as cascodes, to achieve a higher gain and are matched reactively. The differential input is also dc-coupled and biased over the CMF, which ensures an identical base-emitter voltage at both transistors and improves the device matching and the rejection of the odd harmonics.”), and the second amplifier unit amplifies the second harmonic of the signal passing through the first bandpass filter to output the amplified second harmonic through the second output impedance matching unit (the second stage doubler rejects the odd harmonics and provides gain for the even ones…the second harmonic of the signal input from the bandpass filter is amplified to produce the quadrupled frequency).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the second stage frequency doubler of Starke in the frequency quadrupler of Chung, to achieve the benefit of implementing a doubler of low complexity that exhibits improved fundamental suppression (Starke, section II, para. 3).
Regarding claim 4, as best understood based on the 35 U.S.C. 112(b) rejection made above, Chung in view of Starke disclose the frequency quadrupler of claim 3, and Chung continues to disclose, in figure 4, wherein the second bandpass filter (section II, para. 3, “another switchable bandpass filter is sued at the output”…switchable bandpass filter depicted by figure 4) is configured by connecting a second inductor and a second capacitor in parallel (top inductor and 290 fF capacitor connected in parallel), and a second additional capacitor and a second additional switching element are connected in parallel to the second capacitor (top transistor with connected capacitor are connected in parallel to the 290fF capacitor), and when the second additional switching element is turned off (section III, para. 2, “when the CMOS switches are OFF”), a higher frequency band signal passes therethrough than when the second additional switching element is turned on (section IV, para. 3, “when switches are ON, the passband of the two bandpass filters are reduced”…i.e., when the switches are OFF, a higher frequency band signal passes therethrough…for the second BPF it has an increased passband from 16-20 GHz to 16-26 GHz).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Consolazio et al. (US 6,057,740) [Figure 1. Discloses a method and a stable local oscillator system for providing a signal centered at a frequency of interest to a radio frequency (RF) converter. The method includes the following steps: (a) generating an output signal which comprises a fundamental signal centered at a fundamental frequency and a harmonic signal centered at the frequency of interest which is equal to an integral multiple of the fundamental frequency; (b) amplifying the output signal such that the harmonic signal is amplified more than the fundamental signal; and (c) bandpass filtering the amplified output signal such that the amplified fundamental signal is substantially suppressed and the amplified harmonic signal is used as a local oscillator in the RF converter. An example is given for the case where the fundamental frequency is 1.67 gigahertz (GHz), and the frequency of interest is 3.34 GHz which is the second harmonic.]
Balardeta et al. (US 6,657,464 B1) [Figure 1. Discloses A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal. The PLL further includes a multiplexer configured for initially receiving the first error signal until the frequencies of the first divided VCO output signal feedback signal and the second reference signal match, and thereafter for receiving the second error signal, and to provide the first or second error signal to the filter.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J PERENY/ Examiner, Art Unit 2836
Prosecution Insights