DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 2 and analogous claim 7:
Claim 2, from which claim 3 depends, recites that “the memory controller and the data buffer respectively comprise a modulation and demodulation circuit”. Claim 2 therefore positively requires two modulation and demodulation circuits, one in the memory controller and one in the buffer. However, claim 2 goes on multiples times to recite “the modulation and demodulation circuit” in the singular. It is therefore unclear whether claim 2 is referring to both modulation and demodulation circuits in each of the memory controller and the data buffer, respectively, or whether it is only referring to one of them. For this reason, the scope of the claim cannot be determined and the claim is indefinite. The Examiner suggests specifically referring to both modulation and demodulation circuits or specifying which of the two the limitations are referring to.
Regarding claim 3:
Claim 2, from which claim 3 depends, recites that “the memory controller and the data buffer respectively comprise a modulation and demodulation circuit”. Claim 2 therefore positively requires two modulation and demodulation circuits, one in the memory controller and one in the buffer. However, claim 3 subsequently refers in the singular to “the modulation and demodulation circuit” and recites both “when the non-return-to-zero modulation and demodulation circuit is located in the memory controller” and “when the non-return-to-zero modulation and demodulation circuit is located in the data buffer, the data signal to be modulated is the second data signal”. Because claim 2 previously introduced two distinct modulation and demodulation circuits, it is unclear which of these two circuits is referenced by the singular expression, “the modulation and demodulation circuit”.
Moreover, the conditional language in claim 3 appears to treat the modulation and demodulation circuit as a single circuit that may alternatively be located in either the memory controller or the data buffer. This is inconsistent with the requirement from claim 2 that the memory controller and the data buffer each comprise a respective modulation and demodulation circuit. Accordingly, it is unclear whether claim 3 requires that there be only a singular modulation and demodulation circuit that is alternatively located in one of the memory controller or the buffer or whether the requirement from claim 2 that there are two still controls. In the case that there are still two, Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
The Examiner suggests removing the conditional language and instead simply referring to characteristics/configuration of each of “the modulation and demodulation circuit within the memory controller” and “the modulation and demodulation circuit within the data buffer” as appropriate.
Regarding claims 3-4:
Claims 3-4 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2024/0012443 A1 (Lee) as evidenced by the article by Nitin Bagwath, “The Back and Forth of the DDR Data Bus”, 13 September 2017, Siemens, as preserved by the Internet Archive on 05 December 2022, pg. 1 (Bagwath) in further view of US Patent Application Publication No. US 2003/0206046 A1 (To) in further view of US Patent Application Publication No. US 2009/0033364 A1 (Skerlj).
Regarding claim 1 and analogous claims 5 and 6:
Lee teaches, a memory system (1000), comprising: a memory controller (1100); a memory (memory devices (MD1-9) of the memory module (2000), which are examples of memory module (1200) [Figs. 1 and 15]); and a data buffer (DB 1-9), coupled between the memory controller and the memory ((DB 1-9) buffer signals between the memory controller provided to the pins (2201), which are then provided by the buffer (DB1-9) to the memory devices (MD 1-9) [Figs. 1 and 15] [0162-0164]. A processor of the host (i.e., external memory controller) provides the data for writing to the memory to a memory controller, which then transmits the data (i.e., modulates the data signal) to the memory module [0027] [0167] [Fig. 16]. Wherever the signals are sent or received from each of the data buffer and the memory controller are interpreted as ports), and configured to buffer data interacted between the memory controller and the memory (by disclosing that the data buffers (DB 1-9) buffer data between the memory controller (1100) and the memory devices (MD 1-9) [0162-0164] [0166]) wherein the memory controller and the data buffer are coupled to each other via a first data bus (the memory controller (1100) is coupled to the data buffers (DB 1-9) with DQ buses (2202) (a first data bus) and a first data strobe signal bus (the pins (2201) receive DQS signals from the memory controller (1100) as well, which are also provided to the data buffers (DB 1-9) on a signal path (i.e., on a first data strobe signal bus) [0162-0166]), the first data bus being configured to transmit a first data signal (the DQ signals paths between the memory controller (1100) and data buffers (DB 1-9) receive write data signals from the memory controller (1100) and provide read data signals from the memory devices (MD 1-9) [0162-0166]), and the first data strobe signal bus being configured to transmit a first data strobe signal for sampling control of the first data signal (the DQS signal path between the memory controller (1100) and the buffer device (DB 1-9) provides a first data strobe signal [Fig. 15] for sampling control of the first data signal as evidenced by Bagwath, which explains that DQS signals of a respective lane are used to synchronize the sampling of the DQ signals on respective lane on the rising and falling edges of the respective strobe (DQS) signal [Bagwath, ¶¶3-5]), wherein the first data bus and the first data strobe signal bus are both bidirectional signal buses (by disclosing that the DQ and DQS signal paths between the memory controller (1100) and the data buffer (DB 1-9) provide data and strobe signals in both a write and read direction from/to the memory controller (1100) and memory devices (MD 1-9) (i.e., bidirectional) [0164-0166]); and wherein the memory and the data buffer are coupled to each other via a second data bus and a second data strobe signal bus (by disclosing that the data buffers (DB 1-9) may buffer the received DQ and DQS signals from the memory controller (1100) or the memory devices (MD 1-9) and then provide the buffered signals to the memory devices (MD 1-9) or the memory controller (1100) (i.e., the signal paths that provide the signals between the memory devices and the buffer device are interpreted as a second data bus and a second data strobe signal bus) [0162-0166] [Fig. 15]) the second data bus being configured to transmit a second data signal (the DQ signal paths between the memory devices (MD 1-9) and the data buffer (DB 1-9) transmit read and write data to/from the memory controller (1100) and the memory devices (MD 1-9) (i.e., configured to transmit a second data signal) [0162]), and the second data strobe signal bus being configured to transmit a second data strobe signal for sampling control of the second data signal (the DQS signal path between the memory device (MD 1-9) and the buffer device (DB 1-9) provides a first data strobe signal [Fig. 15] for sampling control of the second data signal as evidenced by Bagwath, which explains that DQS signals of a respective lane are used to synchronize the sampling of the DQ signals on respective lane on the rising and falling edges of the respective strobe (DQS) signal [Bagwath, ¶¶3-5]), and the second data strobe signal bus is a bidirectional signal bus (by disclosing that the DQ and DQS signal paths between the memory devices (MD 1-9) and the data buffer (DB 1-9) provide data and strobe signals in both a write and read direction from/to the memory controller (1100) and memory devices (MD 1-9) (i.e., bidirectional) [0164-0166]).
Lee does not explicitly disclose, but To teaches that both the first data bus and the first data strobe signal bus are differential busses and wherein the second data bus is a single-ended data bus, and the second data strobe signal bus is a single-ended signal bus (by teaching that a control interface (104) communicates data from a memory controller (130) to memory units (106) of a memory module (132) through a buffer (140). The control interface (104) of the memory controller (130) communicates by transmitting data to the buffer (140) using a differential bus (121). The buffer (140) may then convert the differential output signals to single-ended output signals for providing the data over a single-ended bus (120) to the memory interface (108) of the memory units (106). Similarly, memory interface (108) of the memory units (106) may transmit data from the memory units (106) to the memory controller (130) through a buffer (140). The memory interface (108) of the memory units (106) transmits data to the buffer (140) using a single-ended bus (120). The buffer (140) may then convert the single-ended output signals to differential output signals for providing the data over a differential bus (121) to the control interface (104) of the memory controller (130) [Fig. 1] [0019-0022].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first data bus and the first data strobe signal bus connecting the memory controller to the data buffer as taught by Lee as evidenced by Bagwath to be differential signal busses as taught by To, and to have modified the second data bus and the second data strobe signal bus connecting the data buffer to the memory device as taught by Lee as evidenced by Bagwath to be single-ended signal busses as taught by To, such that the data buffer converts between single-ended and differential signals for communication between the memory controller and the memory devices as taught by To.
One of ordinary skill in the art would have been motivated to make this modification because the memory units are often pin limited and the single-ended signaling reduces a necessary pin count as each bit of data can be communicated with a single signal output as taught by To in [0004] [0021]. Furthermore, using differential signaling from the memory controller to the buffer is advantageous because it can operate at higher frequencies and results in higher overall signal integrity as taught by To in [0022].
Lee as evidenced by Bagwath in further view of To does not explicitly disclose, but Skerlj teaches and the second data strobe bus is a differential signal bus (by teaching that it is common practice in memory interfaces to make use of differential signaling for timing critical signals such as clocks or strobes, and to use single-ended signaling for data signals in order to keep the design compact and to save board real estate [0002]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the single-ended DQS bus (but not the DQ data signals) routed from the buffer to the memory units as taught by Lee as evidenced by Bagwath in further view of To to instead be a differential bus as taught by Skerlj.
One of ordinary skill in the art would have been motivated to make this modification because it is common practice to use differential signaling for timing critical signals such as the DQS strobe, but to use single-ended signaling for data lines to save board real estate as taught by Skerlj in [0002] and the differential signaling has higher signal integrity as taught by To [0022].
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as evidenced by Bagwath in further view of To in further view of Skerlj in further view of the lecture notes from Sam Palermo, “ECEN689: Special Topics in High Speed Links Circuits and Systems” Spring 2010, Texas A&M University, Analog & Mixed-Signal Center, pgs. 1-18 (Palermo).
Regarding claim 2 and analogous claim 7:
The memory system of claim 1 is made obvious by Lee as evidenced by Bagwath in further view of To in further view of Skerlj (Lee-Bagwath-To-Skerlj).
Lee-Bagwath-To-Skerlj further makes obvious wherein the memory controller and the data buffer respectively comprise a modulation and demodulation circuit, which is configured to modulate or demodulate the first data signal (the memory controller and data buffer can transmit binary data via differential signal pairs (i.e., perform “modulation”) and can receive and interpret the signals communicated on the differential signal pairs as binary bits of data (i.e., “demodulation”) as taught by the combination of Lee-Bagwath-To-Skerlj as performed in the analysis of claim 1).
Lee does not explicitly disclose, but Palermo teaches, wherein the modulation and demodulation circuit is a non-return-to-zero modulation and demodulation circuit or an N-level pulse amplitude modulation and demodulation circuit, where N is an integer greater than 2 (by teaching modulation schemes can include NRZ and PAM-4. The advantages of NRZ modulation are that it is the simplest and most common modulation format, whereas PAM-4 is advantageous because it can transmit 2 bits per symbol [pg. 4]. However, a PAM4 receiver has disadvantages to an NRZ modulation scheme because it has 3x the comparators of an NRZ receiver, has less voltage margin, and is not self-referenced at 0V differential [pgs. 8- 10]. But also, a PAM4 modulation scheme has advantages over NRZ modulation because it can transmit the same amount of data on half the signal lanes or at half the frequency, and has a better Nyquist frequency [pg. 4 and 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transmission of differential data between the memory controller and the data buffer as taught by Lee-Bagwath-To-Skerlj to include using an NRZ or PAM4 modulation scheme as taught by Palermo.
One of ordinary skill in the art would have been motivated to make this modification because NRZ modulation is the simplest and most common modulation format and PAM-4 is also advantageous because it can transmit 2 bits per symbol [pg. 4]. Furthermore, an NRZ modulation scheme is advantageous because it has 3x less comparators than a PAM4 receiver, has more voltage margin, and is self-referenced at 0V differential [pgs. 8- 10]. Moreover, a PAM4 modulation scheme is advantageous because it can transmit the same amount of data on half the signal lanes or at half the frequency, and has a better Nyquist frequency as taught by Palermo on [pgs. 4 and 6].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee-Bagwath-To-Skerlj in further view of Palermo in further view of US Patent Application Publication No. US 2004/0124888 A1 (Radelinow).
Regarding claim 3:
The memory system of claim 2 is made obvious by Lee-Bagwath-To-Skerlj in further view of Palermo.
Lee-Bagwath-To-Skerlj in further view of Palermo makes obvious, the data signal to be modulated is a data signal transmitted from an external controller to the memory controller (through the analysis performed for claim 1 that a processor of the host provides the data for writing to the memory to a memory controller, which then transmits the data (i.e., modulates the data signal) to the memory module (Lee, [0027] [0167] [Fig. 16])) the data signal to be modulated is the second data signal (through the analysis performed for claim 1 that the data buffer would convert the single ended signal from the memory to the differential signal to be provided to the memory controller) wherein the modulation and demodulation circuit is a non-return-to-zero modulation and demodulation circuit (through the analysis performed for claim 2) and the first data signal comprises an in-phase signal and an inverted signal (through the analysis performed for claims 2 by To teaching that the signal should be a differential signal (i.e., an in-phase and an inverted signal)).
Lee-Bagwath-To-Skerlj in further view of Palermo does not explicitly disclose, but Radelinow teaches, and the non-return-to-zero modulation and demodulation circuit comprises: a first D flip-flop configured to generate the in-phase signal (by teaching the FF3 used to generate the signal Ā [Fig. 1]), comprising: a first data input terminal configured to receive a data signal to be modulated (FF3 receives the data signal, DATA, to be modulated into an NRZ differential signal (see [Figs. 1 & 5]), wherein when the non-return-to-zero modulation and demodulation circuit is located in the memory controller (by teaching that these flip flops are included within a LVDS driver for transmitting a differential data signal across a copper wire transmission path (i.e., such as the differential signal sent from the memory controller to the data buffer as taught by Lee-Bagwath-To-Skerlj in further view of Palermo) [0001-0002] [0012-0023]) and when the non-return-to-zero modulation and demodulation circuit is located in the data buffer (by teaching that these flip flops are included within a LVDS driver for transmitting a differential data signal across a copper wire transmission path (i.e., such as the differential signal sent from the buffer to the memory device as taught by Lee-Bagwath-To-Skerlj in further view of Palermo) [Fig. 1] [0001-0002] [0012-0023]) a first clock input terminal configured to receive a flip-flop clock signal (by disclosing the clock input terminal C on FF3 that receives the clock signal CLK [Fig. 1]); a first output terminal configured to selectively output a signal having the same logic level as the data signal to be modulated based on the state of the flip-flop clock signal to obtain the in-phase signal (by teaching the output terminal Q of FF3 that outputs the data signal Ā that has the same logic level as the data signal DATA based on the state of the clock signal CLK input to the clock input terminal C of FF3 [Fig. 1]); an inverter configured to receive the data signal to be modulated and invert the data signal to be modulated to output an initial inverted data signal (by teaching the inverter IV1 that inverts the data signal DATA, which is the signal to be modulated into the differential signal A and Ā in [Fig. 1]); and a second D flip-flop configured to generate the inverted signal (FF1, which generates the signal A, which is inverted from Ā [Fig. 1]), comprising: a second data input terminal coupled to the inverter to receive the initial inverted data signal output from the inverter (FF1 includes input data terminal D, which is coupled to the inverter IV1, which receives the inverted data signal DATA from the inverter IV1[Fig. 1]); a second clock input terminal (FF1 includes input clock terminal C [Fig. 1]) configured to receive the flip-flop clock signal (the input clock terminal C receives the clock signal CLK); a second output terminal configured to selectively output a signal having the same logic level as the initial inverted data signal based on the state of the flip-flop clock signal to obtain the inverted signal (the FF1 includes the output terminal Q that selectively outputs the signal A, which has the same logical level as the initial inverted data signal DATA output from the inverter IV1 based on the state of the clock signal CLK input to the clock input terminal C of FF1 to obtain the inverted signal A [Fig. 1]. This method of generating the differential signal can then be used with a pre-emphasis technique to improve the eye diagram of the transmitted differential signal [0012-0036]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the drivers for the differential signals transmitted from the memory controller and from the memory buffer as taught by Lee-Bagwath-To-Skerlj in further view of Palermo to include two flip flops to generate each differential signal, with one of the flip flops being input the data signal and the other the inverted data signal as taught by Radelinow and to use of the flip flop configuration to enable pre-emphasis on the generated differential signal as taught by Radelinow.
One of ordinary skill in the art would have been motivated to make this modification because with this method of generating the differential signal with the inverter placed on a flip flop’s input, the differential output signals are not displaced in time due to extra inverter delay (for example, if it were rather placed on its output) because the single-ended to differential conversion is done in the digital domain with positive edge-triggered flip flops as taught by Radelinow in [0033], furthermore, the flip flop configuration used to generate the differential signal allows for pre-emphasis of the transmitted signal, which improves the eye diagram of the generated signal as taught by Radelinow in [0036-0042].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow in further view the article by Chau Tran et. al., “A Low Power, Low Cost, Differential Input to a Single-Ended Output Amplifier”, September 2017, Analogue Dialogue 51-09, Rarely Asked Questions – Issue 145, pgs. 1-2 (Tran).
Regarding claim 4:
The memory system of claim 3 is made obvious by Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow.
Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow do not explicitly disclose, but Tran teaches, wherein the non-return-to-zero modulation and demodulation circuit further comprises a differential amplifier (by teaching the differential input to single-ended output amplifier [Fig. 1] (i.e., which could be used in the buffer to perform the conversion from differential to single-ended signaling as taught by Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow)) the differential amplifier comprises: an in-phase input terminal coupled to a signal bus of the first data bus configured to transmit the in-phase signal), and configured to receive the in-phase signal (the inputs Vin_1 and Vin_2 receive the differential signal, which includes a transmitted in-phase signal and an inverted signal [Fig. 1] (i.e., from the memory controller as taught by Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow) an inverted input terminal, coupled to a signal line of the first data bus configured to transmit the inverted signal, and configured to receive the inverted signal (the inputs Vin_1 and Vin_2 receive the differential signal, which includes a transmitted in-phase signal and an inverted signal (i.e., from the memory controller as taught by Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow) and an output terminal configured to output a gain signal of the differential signal between the in-phase signal and the inverted signal (by teaching Vout, which, outputs a gain signal of the differential signal between the in-phase signal and the inverted signal [Fig. 1] [Fig. 2]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conversion from differential to single-ended signals in the data buffer as taught by Lee-Bagwath-To-Skerlj in further view of Palermo in further view of Radelinow to be performed with the two op amp solution as taught by Tran.
One of ordinary skill in the art would have been motivated to make this modification because the circuit offers a combination of excellent distortion with low quiescent current and is low cost. Furthermore, the circuit offers common-mode rejection with adjustable gain as taught by Tran in [pg. 1, column 2, ¶1-2] [pg. 2, column 2, last ¶].
Conclusion
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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