DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US Patent Number 8,006,062, hereinafter “Cheng”) in view of Natu et al. (US Publication Number 2019/0102325, hereinafter “Natu”).
4. As per claim 1, Natu a memory device (235 figures 2a and 2b) comprising: a substrate (DIMM body of module 235, column 3, lines 5 – 13); a plurality of memory units (240, figures 2a and 2b), disposed on the substrate (on the DIMM, 235, figures 2a and 2b); and a serial presence detection module (SPD 245, figures 2a and 2b), disposed on the substrate and electrically connected to the memory units (structure of 235 with respect to 240 and 245, figures 2a and 2b, column 2, line 47, column 3, line 33, ), which is also connected to a storage component (figures 2a and 2b, SPD format 252 within SPD memory 245 with identifier 255) storing at least a first memory setting data (SPD profiles 260, figure 2a, column 3, line 36) and a second memory setting data (second profile 260, figures 2a and 2b, of the plurality of SPD profiles with associated settings column 3, lines 14 - 57) supporting the first and second processors respectively (concurrently storing standard compliant configuration and pre-loaded extended SPD format for two different optimized modes, figures 4a and 4b, SPD map 250 and 255, column 5, lines 3 – 15).
Cheng does not appear to explicitly disclose a memory device supporting multiple serial presence detection settings, which is applied for supporting a first processor and a second processor, which are different computational circuits, wherein the serial presence detection module reads the first memory setting data to the first processor when the serial presence detection module is electrically connected to the first processor, and the serial presence detection module reads the second memory setting data to the second processor when serial presence detection module is electrically connected to the second processor.
However, Nato discloses teaches a memory device (memory, 206, figure 1, 296, figure 10) supporting multiple serial presence detection settings (SPD paragraph 20), which is applied for supporting a first processor (1070, figure 8) and a second processor (1080, figure 8), which are different computational circuits (distinction between processors and how they communicate with one another seen in 100, figure 8), wherein the serial presence detection module (SPD used to read management partition 214, paragraph 20) reads the first memory setting data (via policy manager 212, paragraph 18) to the first processor when the serial presence detection module is electrically connected to the first processor (SPD processor handling, paragraphs 18 to 21), and the serial presence detection module reads the second memory setting data to the second processor when serial presence detection module is electrically connected to the second processor (second processor via SKU, paragraphs 14, 18 and 44, total capacity per processor differentiation seen in paragraph 14, where data structure includes a number of different groups of rules corresponding to different stock keeping units with respect to processor presence, paragraphs 44 – 51).
Cheng and Natu are analogous art because they are from the same field of endeavor of SPD handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Cheng and Natu before him or her, to modify the processing mechanism of Cheng to include the structural elements of Natu because it would enhance the SPD processing.
One of ordinary skill would be motivated to make such modification in order to enhance data integrity in the system (paragraphs 12 and 13). Therefore, it would have been obvious to combine Natu with Cheng to obtain the invention as specified in the instant claims.
5. Cheng modified by the teachings of Natu as seen in claim 1 above, as per claim 2, Chen teaches a memory device, wherein the serial presence detection module (245, figure 2) further includes a default memory setting data (Standard SPD address map bytes 250, figures 2a and 2b) supporting both the first and second processors (CPU 205, GPU 220, figures 2a and 2b), the serial presence detection module reads one of the first memory setting data (parameter profiles 260, seen in figure 4a and 4b) and the default memory setting data to the first processor when the serial presence detection module is electrically connected to the first processor, and the serial presence detection module reads one of the second memory setting data and the default memory setting data to the second processor when the serial presence detection module is connected to the second processor (plurality of profiles via 260, with electrically connected structure between SPD and processors where module concurrently stores compliant configuration information, the DIMM remains JEDEC compliant BIOS handling, column 3, lines 14 – 57).
6. Cheng modified by the teachings of Natu as seen in claim 1 above, as per claim 3, Natu teaches a memory device, where the first processor is one of Intel's and AMD's central processing units (Natu utilizes Intel processors, figure 1).
7. Cheng modified by the teachings of Natu as seen in claim 1 above, as per claim 4, Natu teaches a memory device, wherein the second processor is one of Intel's and AMD's central processing units (Natu utilizes Intel processors, figure 1).
8. Cheng modified by the teachings of Natu as seen in claim 1 above, as per claim 5, Natu teaches a memory device, wherein the substrate and the memory units match a protocol of DDR5 memory (DDR5, paragraph 61).
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fryman/Ahuja/Misra had teachings of SPD multiprocessor handling.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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