Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant’s filing on 27 May 2025. Claims 1-25 are presently pending and under consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-22, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujimoto (US 2024/0311010 A1, hereinafter Fujimoto).
Regarding claim 1, Fujimoto discloses a memory apparatus, comprising: one or more controllers (See Fujimoto, Fig. 1 disclosing NVMe controller 11 and [0019], The NVMe™ controller 11 controls a system memory 23 and the flash memory 12 via PCIe buses) configured to:
receive, from a host system, configuration information indicating one or more performance limits for respective memory operations of one or more memory operations (See Fujimoto, [0027] the host 2 can know the power consumption of each power state from the power state register, and can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command. For example, the host 2 can control the temperature of the memory device 1 by urging the memory device 1 to select a power state with lower performance than the power state set at that time to reduce the power consumption (heat generation) of the memory device 1); and
perform the one or more memory operations in accordance with the one or more performance limits (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state, or in other words, perform read/write operations at power state zero).
Regarding claim 2, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more performance limits indicate values of respective thresholds from one or more thresholds (See Fujimoto, [0026] disclosing multiple power states PS0, PS1, PS2, and PS3, each with power consumption and [0027], disclosing an allowable temperature), wherein the one or more thresholds are associated with respective performance parameters from one or more performance parameters (See Fujimoto, [0026] disclosing multiple power states PS0, PS1, PS2, and PS3, each with respective transfer rates and power consumption and [0027], disclosing an allowable temperature), and
wherein the one or more controllers, to perform the one or more memory operations, are configured to: limit values of the one or more performance parameters, for the one or more memory operations, to be less than or equal to corresponding thresholds of the one or more thresholds (See Fujimoto, [0058] For example, in the case of “Gen3 1-lane”, the maximum performance for stream recording may be selected from “150 MB/s”, “300 MB/s”, “450 MB/s”, and “600 MB/s”. For example, when manufactured with “600 MB/s” considered as the maximum performance for stream recording, the memory device 1 can also support “450 MB/s”, “300 MB/s”, and “150 MB/s”. For example, in order for the host to perform stable stream recording with the performance of “600 MB/s” for a long time, it is necessary to comprise the heat dissipation mechanism 25 that can dissipate the power consumption of the memory device listed in power state PS0, and it is necessary to prevent the temperature rise above a certain level from occurring for continuous memory access in “600 MB/s”).
Regarding claim 3, Fujimoto disclosed the memory apparatus of claim 2 as above. Fujimoto further discloses wherein the one or more performance parameters include at least one of: a throughput parameter, or a latency parameter (See Fujimoto [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1).
Regarding claim 4, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more performance limits include one or more data transfer rate limits for the one or more memory operations (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state).
Regarding claim 5, Fujimoto disclosed the memory apparatus of claim 4 as above. Fujimoto further discloses wherein the one or more controllers, to perform the one or more memory operations, are configured to: adjust one or more speeds of the one or more memory operations to meet the data transfer rate limit (See Fujimoto [0060] the NVMe™ controller 11 performs throttling. The performance of the connection interface itself between the NVMe™ controller 11 and the flash memory 12 is determined by the bus width and the clock frequency. Throttling is, for example, a method of controlling the frequency of data transfer performed on this connection interface, which can be considered as a method of adjusting the utilization rate of the connection interface. In other words, when the maximum performance of the connection interface is 1,000 MB/s, the memory device 1 supporting the performance of “600 MB/s” is adjusted by throttling such that the performance is slightly higher than “600 MB/s” under worst-case conditions to consider margin during the stream recording. When operating at the performance of “450 MB/s”, “300 MB/s”, or “150 MB/s”, the memory device 1 is adjusted such that the performance is slightly higher than a specified value by throttling).
Regarding claim 6, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more performance limits are associated with a time window, and wherein one or more performance parameters associated with the one or more memory operations satisfy the one or more performance limits over the time window (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state, or in other words a threshold value of xxxMB or some maximum temperature reading associated with the power state, over a time window of at least one second).
Regarding claim 7, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more performance limits include different performance limits for different memory operations of the one or more memory operations (See Fujimoto, [0088] For example, if the number of power states is three, the host 2 can recognize power state PS0=“450 MB/s”, power state PS1=“300 MB/s”, and power state PS2=“150 MB/s”. As a result, for example, the host 2 can select power state PS0 for recording in high quality where “450 MB/s” is required, select power state PS1 for recording in medium quality where “300 MB/s” is sufficient, and select power state PS2 for low quality recording where “150 MB/s” is sufficient, or in other words, different power consumption for different types of memory write operations).
Regarding claim 8, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more controllers, to receive the configuration information, are configured to: receive an information element for a performance limit of the one or more performance limits (See Fujimoto, [0027] For example, the host 2 can control the temperature of the memory device 1 by urging the memory device 1 to select a power state with lower performance than the power state set at that time to reduce the power consumption (heat generation) of the memory device 1.), wherein the information element indicates:
a memory operation, of the one or more memory operations, associated with the performance limit (See Fujimoto, [0070], disclosing SPL values having an associated data transfer rate),
a value of the performance limit (See Fujimoto [0097] The SPL register value can be used as one of methods for recognizing the class performance standard version of the host. In the SD Express™ specification of the SD™ standard, 1.8 W, 2.5 W, 2.8 W, 3.2 W, and 4.0 W), and
a time window over which the value is to be met for performance of the one or more memory operations (See Fujimoto, [0058] “in order for the host to perform stable stream recording with the performance of “600 MB/s” for a long time, it is necessary to comprise the heat dissipation mechanism 25 that can dissipate the power consumption of the memory device listed in power state PS0, and it is necessary to prevent the temperature rise above a certain level from occurring for continuous memory access in “600 MB/s”. Normally, the temperature is set not to exceed the upper temperature limit for safe use of flash memory”, or in other words, a time window equivalent to the lifetime of the device).
Regarding claim 9, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more memory operations are supported use cases for the memory apparatus (See Fujimoto, [0058] performance for stream recording may be selected from “150 MB/s”, “300 MB/s”, “450 MB/s”, and “600 MB/s”. For example, when manufactured with “600 MB/s” considered as the maximum performance for stream recording, the memory device 1 can also support “450 MB/s”, “300 MB/s”, and “150 MB/s”).
Regarding claim 10, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more memory operations include at least one of a sequential read operation, a sequential write operation, a random read operation, or a random write operation (See Fujimoto, [0055] options of the data transfer rate are predefined as, for example, the SD Express™ specifications of the SD™ standard, for stream recording” or in other words, sequential write operations).
Regarding claim 11, Fujimoto disclosed the memory apparatus of claim 1 as above. Fujimoto further discloses wherein the one or more memory operations include at least one of: a write-booster operation, or a non-write-booster operation (See Fujimoto, [0088] “For example, if the number of power states is three, the host 2 can recognize power state PS0=“450 MB/s”, power state PS1=“300 MB/s”, and power state PS2=“150 MB/s”. As a result, for example, the host 2 can select power state PS0 for recording in high quality where “450 MB/s” is required, select power state PS1 for recording in medium quality where “300 MB/s” is sufficient, and select power state PS2 for low quality recording where “150 MB/s” is sufficient”, where high quality is equivalent to applicant’s write booster operation and low quality is equivalent to applicant’s non-write-booster operation).
Regarding claim 12, Fujimoto discloses a host system, comprising: one or more controllers configured (See Fujimoto, Fig. 1 disclosing host 2 with system controller 22 and [0043] The system controller 22 controls the processor 21 accessing to the system memory 23 and also controls the processor 21 accessing to the memory device 1), to:
transmit, to a memory apparatus, a request for supported memory operations of the memory apparatus (See Fujimoto, [0027] By associating the performance with the power state, the host 2 can read the power state register of the memory device 1 with the NVMe™ command and can recognize the performance supported by the memory device 1 by the contents of this power state register, or in other words, the host transmit a read request for the power state(s) supported);
receive, from the memory apparatus, capability information indicating one or more supported memory operations (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1 and [0027] By associating the performance with the power state, the host 2 can read the power state register of the memory device 1 with the NVMe™ command and can recognize the performance supported by the memory device 1 by the contents of this power state register, or in other words, the host transmit a read request for the power state(s) supported and receives the power states for read and write operations supported by the memory device); and
transmit, to the memory apparatus, configuration information indicating one or more performance limits for at least one supported memory operation of the one or more supported memory operations (See Fujimoto, [0027] disclosing the host “can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command”).
Regarding claim 13, Fujimoto disclosed the host system of claim 12 as above. Fujimoto further discloses wherein configuration information indicates performance limits, of the one or more performance limits, for respective supported memory operations of the one or more supported memory operations (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state).
Regarding claim 14, Fujimoto disclosed the host system of claim 12 as above. Fujimoto further discloses wherein a performance limit, of the one or more performance limits, indicates a threshold value for a performance parameter that is not be exceeded over a time window during a performance of a supported memory operation of the one or more supported memory operations (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state, or in other words a threshold value of xxxMB or some maximum associated temperature reading associated with the power state, over a time window of at least one second and/or [0058] “Normally, the temperature is set not to exceed the upper temperature limit for safe use of flash memory”, or in other words, a time window equivalent to the lifetime of the device).
Regarding claim 15, Fujimoto disclosed the host system of claim 12 as above. Fujimoto further discloses wherein the one or more performance limits include an input-output operations per second (IOPS) limit (See Fujimoto, [0026] For example, when the memory device 1 supports the performance of four data transfer rates “600 MB/s”, “450 MB/s”, “300 MB/s”, and “150 MB/s” between the host 2 and the memory device 1, four power states PS0=600 MB/s, PS1=450 MB/s, PS2=300 MB/s, and PS3=150 MB/s are generally defined. In the memory device 1, power state PS0 is selected in an initial state).
Regarding claim 16, Fujimoto disclosed the host system of claim 12 as above. Fujimoto further discloses wherein the one or more controllers are further configured to: transmit, to the memory apparatus, a communication modifying a value of at least one performance limit of the one or more performance limits (See Fujimoto, [0027] disclosing the host “can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command”).
Regarding claim 17, Fujimoto disclosed the host system of claim 12 as above. Fujimoto further discloses wherein the one or more supported memory operations include at least one of: one or more write operations, or one or more read operations (See Fujimoto, [0042] “the memory device 1 of the embodiment prepares the power state set [2] 115 for stream recording in addition to the conventional power state set, i.e., the power state set [1] 114 for default” or in other words, one or more write operations).
Regarding claim 18, Fujimoto discloses a method, comprising: transmitting, by a memory apparatus and to a host system, capability information indicating one or more supported memory operations of the memory apparatus (See Fujimoto, [0027] By associating the performance with the power state, the host 2 can read the power state register of the memory device 1 with the NVMe™ command and can recognize the performance supported by the memory device 1 by the contents of this power state register, or in other words, the host reads the power state(s) supported and receives the power states for read and write operations supported by the memory device); and
receiving, by the memory apparatus and from the host system, configuration information indicating one or more performance limits for at least one supported memory operation of the one or more supported memory operations (See Fujimoto, [0027] disclosing the host “can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command”).
Regarding claim 19, Fujimoto disclosed the method of claim 18 as above. Fujimoto further discloses performing an operation for the at least one supported memory operation in accordance with the one or more performance limits (See Fujimoto, [0060], “the NVMe controller performs throttling…as a method of adjusting the utilization rate of the interface…the memory device 1 supporting the performance of “600 MB/s” is adjusted by throttling such that the performance is slightly higher than “600 MB/s” under worst-case conditions to consider margin during the stream recording”).
Regarding claim 20, Fujimoto disclosed the method of claim 19 as above. Fujimoto further discloses wherein performing the operation comprises: adjusting the operation to cause one or more performance parameters for the operation to not exceed the one or more performance limits (See Fujimoto, [0060] In order to prevent the temperature rise above a certain level from occurring during stream recording, the NVMe controller 11 performs throttling. The performance of the connection interface itself between the NVMe controller 11 and the flash memory 12 is determined by the bus width and the clock frequency).
Regarding claim 21, Fujimoto disclosed the method of claim 18 as above. Fujimoto further discloses wherein the configuration information indicates time windows for respective performance limits of the one or more performance limits, wherein the time windows indicate durations over which the memory apparatus is to meet the one or more performance limits (See Fujimoto, [0070], disclosing SPL values having an associated data transfer rate, [0097] The SPL register value can be used as one of methods for recognizing the class performance standard version of the host. In the SD Express™ specification of the SD™ standard, 1.8 W, 2.5 W, 2.8 W, 3.2 W, and 4.0 W and [0058] “in order for the host to perform stable stream recording with the performance of “600 MB/s” for a long time, it is necessary to comprise the heat dissipation mechanism 25 that can dissipate the power consumption of the memory device listed in power state PS0, and it is necessary to prevent the temperature rise above a certain level from occurring for continuous memory access in “600 MB/s”. Normally, the temperature is set not to exceed the upper temperature limit for safe use of flash memory”, or in other words, a time window equivalent to the lifetime of the device).
Regarding claim 22, Fujimoto discloses a system, comprising: a host system (See Fujimoto Fig. 1 disclosing host 2 and [0017] FIG. 1 also shows an example of a configuration of a host 2);
a memory apparatus (See Fujimoto Fig. 2 disclosing memory device 1 and [0017] FIG. 1 is a view showing an example of a configuration example of a PCIe™/NVMe™ memory device 1);
a host interface between the host system and the memory apparatus (See Fujimoto, [0015] In general, according to one embodiment, a memory card includes a nonvolatile memory and a controller. The controller is connectable to a host via an interface conforming to PCI Express™ (PCIe™) standard); and
one or more controllers configured to: communicate, via the host interface and to the host system, capability information of the memory apparatus indicating one or more supported memory operations of the memory apparatus (See Fujimoto, Fig. 1 disclosing NVMe controller 11 and [0019], The NVMe™ controller 11 controls a system memory 23 and the flash memory 12 via PCIe buses and [0027] By associating the performance with the power state, the host 2 can read the power state register of the memory device 1 with the NVMe™ command and can recognize the performance supported by the memory device 1 by the contents of this power state register. In addition, the host 2 can know the power consumption of each power state from the power state register, and can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command); and
communicate, via the host interface and to the memory apparatus, configuration information indicating one or more performance limits for at least one supported memory operation of the one or more supported memory operations (See Fujimoto, [0027] disclosing the host “can specify any one of one or more power states set in the memory device 1 and request the memory device 1 to select the specified power state by the NVMe™ command”).
Regarding claim 24, Fujimoto disclosed the system of claim 22 as above. Fujimoto further discloses wherein the one or more controllers are further configured to: perform, by the memory apparatus, an operation for the at least one supported memory operation in accordance with the one or more performance limits (See Fujimoto, [0060], “the NVMe controller performs throttling…as a method of adjusting the utilization rate of the interface…the memory device 1 supporting the performance of “600 MB/s” is adjusted by throttling such that the performance is slightly higher than “600 MB/s” under worst-case conditions to consider margin during the stream recording”).
Regarding claim 25, Fujimoto disclosed the system of claim 22 as above, Fujimoto further discloses wherein the capability information and the configuration information are communicated as part of an initialization of the memory apparatus (See Fujimoto, [0015] “The controller performs initialization of the interface cooperatively with the host, determines a maximum performance that can be supported from among a plurality of performance predetermined for stream recording, based on a bus configuration of the interface determined at the interface initialization and a maximum allowable power consumption set during the interface initialization, and generates a data set stored in a power state register specified by the NVMe™ standard, which is a power state set in which each of all performance smaller than the determined maximum performance among the plurality of performance corresponds to a power state, to indicate a list of the performance which can be supported for a host”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Fujimoto (US 2024/0311010 A1, hereinafter Fujimoto) in view of Kurita et al (US 2021/0405900 A1, hereinafter Kurita).
Regarding claim 23, Fujimoto disclosed the system of claim 22 as above. Fujimoto does not further disclose wherein the one or more performance limits indicate latency parameters for respective operation sizes of the at least one supported memory operation.
However, Kurita discloses wherein the one or more performance limits indicate latency parameters for respective operation sizes of the at least one supported memory operation (See Kurita, [0254], “The host 2 may send the write performance degradation acceptable value as an acceptable value designation command. The write performance can be represented by guaranteed throughput (bytes/second), latency (seconds) and the like. The lower value of the guaranteed throughput (bytes/second) and the upper value of the latency (seconds) are sent to the SSD 3 as acceptable values of the degradation”).
Fujimoto and Kurita are analogous art directed to improved guaranteed memory performance techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the multiple power support of Fujimoto with the multiple latencies of Kurita as memory system flexibility and reliability can be increased by having different latencies to accommodate sufficient requested write speed (See Kurita, [0088] and [0254], disclosing different write modes, with different latencies, to maintain guaranteed write speeds).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang (US 2017/0177524 A1) discloses a host acquiring capability supported by a terminal device.
Jung (US 2024/0272830 A1) discloses a storage controller to generate and provide multi-latency information to a host, wherein the multi-latency information includes an indicator representing an internal event and the expected processing times and the expected latencies corresponding to allocation ratios.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDMUND H KWONG whose telephone number is (571)272-8691. The examiner can normally be reached Monday-Friday 10-6 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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