Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant’s filing on 12 February 2025. Claims 1-20 are presently pending and under consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 April 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-10, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choe et al (US 2022/0100669 A1, hereinafter Choe).
Regarding claims 1, 8, and 15, taking claim 1 as exemplary, Choe discloses a system comprising: a memory device (See Choe Fig. 1 disclosing Smart Storage Device 1000 and [0022], “[0022] A smart storage device 1000 may be a data center or an artificial intelligence learning data device according to embodiments of the present disclosure. The smart storage device 1000 may be a semiconductor device capable of performing computations and storing data, such as processing-in-memory (PIM) or computing-in-memory (CIM)”); and
a processing device, operatively coupled with the memory device (See Choe Fig. 1 disclosing accelerator 200 and [0028] “[0028] The accelerator circuit 200 may perform an acceleration computation according to a computation command of the host device 10. According to some embodiments, the accelerator circuit 200 may be a neural network processing unit, an AI accelerator, a CPU, a graphical processing unit (GPU), a digital signal processing unit (DSP), a neural processing unit (NPU), a coprocessor, or another suitable processor”), to perform operations comprising:
receiving, from a host system, a first command to configure an accelerator associated with the memory device (See Choe, [0044] When receiving a command, for example, a computation command from the host device 10, the command decoder circuit 210 decodes the received computation command to extract computation information. The computation information may include, for example, a computation type, an address of data to be computed, or the like), wherein the first command comprises one or more operations (See Choe, [0056], “According to some embodiments, the computation command may include at least one operation to be performed by the accelerator circuit”);
identifying, based on the first command, a command type of the first command (See Choe, [0044] When receiving a command, for example, a computation command from the host device 10, the command decoder circuit 210 decodes the received computation command to extract computation information. The computation information may include, for example, a computation type, an address of data to be computed, or the like);
determining, based on the command type, a first instruction to configure the accelerator to perform the one or more operations comprised by the first command (See Choe, [0044] When receiving a command, for example, a computation command from the host device 10, the command decoder circuit 210 decodes the received computation command to extract computation information); and
sending, to the accelerator, the first instruction, wherein the one or more operations are to be performed by the accelerator according to the first instruction (See Choe, [0048] The computation module 250 may perform acceleration computation according to the decoded computation command).
Regarding claims 2, 9, and 16, taking claim 2 as exemplary, Choe disclosed the system of claim 1 as above. Choe further discloses wherein the command type of the first command is a download command, and wherein the first instruction further comprises an indication to store the one or more operations on a plurality of memory cells of the accelerator addressable by a range of physical addresses (See Choe, [0056] The accelerator circuit 200 extracts computation information by decoding a received computation command CMD1 (step S12). The computation information may include, for example, a computation type, an address of data necessary for the computation, [0057] The accelerator circuit 200 transmits a data access request to the storage controller 300 (step S13), [0059] The storage controller 300 transmits the performance result of the access to the accelerator circuit 200 (step S16). For example, in the case of a data read request, the read data (hereinafter, first data) is returned, and [0060] When receiving a performance result, for example, the read first data (step S17), the accelerator circuit 200 performs coherence processing with the host device 10 to store the data in the accelerator memory 290 (step S18) or in other words, the command is a “download” command and results in the storage of data to accelerator memory).
Regarding claims 3, 10, and 17, taking claim 3 as exemplary, Choe disclosed the system of claim 2 as above. Choe further discloses wherein the processing device is to perform operations further comprising: receiving, from the host system, a second command to configure the accelerator (See Choe, [0056] “The accelerator circuit 200 extracts computation information by decoding a received computation command CMD1 (step S12)” - repeating for a second time or [0064], “when the host device transmits a command CMD2”), wherein the second command references the range of physical addresses at which the one or more operations comprised by the first command is stored (See Choe, [0044], “The computation information may include, for example, a computation type, an address of data to be computed”, or in other words, where the previously computed data can be found);
identifying, based on metadata associated with the second command, a command type of the second command (See Choe, [0044] When receiving a command, for example, a computation command from the host device 10, the command decoder circuit 210 decodes the received computation command to extract computation information. The computation information may include, for example, a computation type, an address of data to be computed, or the like), wherein the command type of the second command is a start command (See Chloe, [0048] The computation module 250 may perform acceleration computation according to the decoded computation command” or in other words, “starts” the computation requested); and
sending, to the accelerator, a second instruction to perform the one or more operations comprised by the first command (See Choe, [0048] The computation module 250 may perform acceleration computation according to the decoded computation command).
Regarding claims 7, 14, and 20, taking claim 7 as exemplary, Choe disclosed the system of claim 1 as above. Choe further discloses wherein each of the processing device and the memory device is connected to the host system via a respective plurality of Compute Express Link (CXL) links (See Choe, Fig. 1 disclosing CXL.cache, CXL.mem, and CXL.io links between smart storage device 1000 and host 10 and [0024] and [0027]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5, 11-12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Choe et al (US 2022/0100669 A1, hereinafter Choe) in view of Ji (US 2025/0291798 A1, hereinafter Choe).
Regarding claims 4 and 11, taking claim 4 as exemplary, Choe disclosed the system of claim 1 as above. Choe does not disclose wherein the command type of the first command is a status command.
However, Ji discloses wherein the command type of the first command is a status command (See Ji, [0055] and [0056], disclosing the host device checking the query plan status for each device).
Choe and Ji are analogous are directed to improved CXL storage, computation, and management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the smart storage device of Choe with the command type of Ji as system performance can be increased by allowing the accelerator/storage device to predict the use of query processing and prepare for task processing and conserve host memory resources and reduce network complexity with the device (See Ji [0058]).
Regarding claims 5, 12, and 18, taking claim 5 as exemplary, Choe disclosed the system of claim 2 as above. Choe further discloses wherein the processing device is to perform operations further comprising: receiving, from the host system, a second command to configure the accelerator (See Choe, [0056] “The accelerator circuit 200 extracts computation information by decoding a received computation command CMD1 (step S12)” - repeating for a second time or [0064], “when the host device transmits a command CMD2”), wherein the second command references the range of physical addresses at which the one or more operations comprised by the first command is stored (See Choe, [0044], “The computation information may include, for example, a computation type, an address of data to be computed”);
identifying, based on metadata associated with the second command, a command type of the second command (See Choe, [0044] When receiving a command, for example, a computation command from the host device 10, the command decoder circuit 210 decodes the received computation command to extract computation information. The computation information may include, for example, a computation type, an address of data to be computed, or the like).
Choe does not disclose wherein the command type of the second command is a status command; and sending, to the accelerator, a second instruction to return a status of performing the one or more operations comprised by the first command.
However, Ji discloses wherein the command type of the second command is a status command (See Ji, [0055] and [0056], disclosing the host device checking the query plan status for each device); and
sending, to the accelerator, a second instruction to return a status of performing the one or more operations comprised by the first command (See Ji, [0036] Referring to FIG. 5, the host device 100 transmits a query for requesting the information or manipulating to the device 200. In order to transmit the query, the host device 100 may control query transmission for each stage and device by referring to the query plan status information QS and [0055] and [0056], disclosing the host device checking the query plan status for each device).
Choe and Ji are analogous are directed to improved CXL storage, computation, and management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the smart storage device of Choe with the command type of Ji as system performance can be increased by allowing the accelerator/storage device to predict the use of query processing and prepare for task processing and conserve host memory resources and reduce network complexity with the device (See Ji [0058]).
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choe et al (US 2022/0100669 A1, hereinafter Choe) in view of Nguyen et al (US 20240152466 A1, hereinafter Nguyen).
Regarding claims 6, 13, and 19, taking claim 6 as exemplary, Chloe disclosed the system of claim 3 as above. Choe further discloses wherein the processing device is to perform operations further comprising: storing, on a second plurality of memory cells of the accelerator addressable by a second range of physical addresses, a computation result of performing the one or more operations (See Choe, [0037] disclosing accelerator memory 290 dedicated to the accelerator circuit and [0047] “The accelerator memory controller 240 may control an operation of the accelerator memory 290. For example, control may be performed so that computation data stored in the accelerator memory 290 is read or deleted, or new computation data is written”).
Choe does not disclose wherein the second command identifies the second plurality of memory cells addressable by the second range of physical addresses.
However, Nguyen discloses wherein the second command identifies the second plurality of memory cells addressable by the second range of physical addresses (See Nguyen, [0050] In FIG. 3B, accelerator 135 may store the output directly in any of shared region 310, private region 315, memory 115, volatile memory 325, or non-volatile storage 330. Accelerator 135 may select the appropriate destination based on criteria such as those discussed above, or processor 135 may use a command via an API of accelerator 135 to specify the desired destination).
Choe and Nguyen are analogous art directed to improved CXL storage, computation, and management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the smart storage device of Choe with the flexible storage location of Nguyen as system performance can be increased by flexibly placing the desired data in different memory locations to avoid the necessity of needing to always first access device local memory of the accelerator and transferring the data to host memory (See Nguyen, [0018]-[0020]).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al (US 20240201858 A1) disclosing receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.
Park et al (US 20240394331 A1) A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDMUND H KWONG whose telephone number is (571)272-8691. The examiner can normally be reached Monday-Friday 10-6 PT.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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