DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 20220075722 A1) in view of Traister (US 20090006719 A1).
Referring to claims 1, 13, and 19, taking claim 1 as exemplary, Liang teaches
A memory apparatus, comprising: one or more controllers configured to: ([Liang abstract, 0029, Fig. 1] exemplary memory device includes a memory controller ) an indication of an amount of internal maintenance operation work to be completed for the memory apparatus, ([Liang abstract, 0024-0025, Figs. 8] adapting garbage collection (GC) operations in a memory device to an estimated device age. memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.) wherein the amount of internal maintenance operation work is based on at least one of: one or more lifespan utilization parameters, or one or more types of additional maintenance operations to be performed by the memory apparatus; ([Liang 0020, 0069-0071, 0075, 0085, 0088, Figs. 6-8] Garbage collection (GC) is an operation to manage memory utilization in a flash memory. The memory controller 610 may include one or more of a flash translation layer (FTL) 612, a device age tracker circuit 614, a garbage collection (GC) controller 616.By way of example and not limitation, two memory management functions are illustrated in FIG. 6, namely GC operation operated by the GC controller 616, and SLC cache configuration operated by the SLC cache controller 618. One or both of the GC operation and the SLC cache configuration may be adapted to a memory usage characteristic, such as a wear-indicated device life expectancy or device age that is produced by the device age tracker circuit 614. Various embodiments of GC control and SLC cache configuration adapted to the wear-indicated device life expectancy device age as discussed in this document may improve balanced memory device performance and device lifetime. At 830, a GC operation may be initiated or adjusted based at least on the wear-indicated device age or life expectancy. FIG. 7 is a block diagram illustrating an example of a device age tracker circuit 710 for tracking a wear-indicated device age or life expectancy. The device age tracker circuit 710 is an embodiment of the device age tracker circuit 614 of FIG. 6. The wear-indicated device age may indicate memory device utilization, such as a light workload that corresponds to memory underuse, or a heavy workload overused that corresponds to memory overuse. FIG. 8 is a flow chart illustrating another method 800 of optimizing memory utilization in a memory device based at least on memory usage characteristic, such as an estimated device life expectancy or wear-indicated device age, according to some examples discussed in the present document.) scheduling information for one or more internal maintenance operations, wherein the scheduling information is based on the amount of internal maintenance operation work; ([Liang 0075, Figs. 7-8] The wear-indicated device age may indicate memory device utilization, such as a light workload that corresponds to memory underuse, or a heavy workload overused that corresponds to memory overuse. GC aggressiveness and/or SLC cache size may be adjusted in accordance with the wear-indicated device age or life expectancy. For example, in case of a lighter workload or an indication of memory underuse, more aggressive GC operations may be performed, and a larger SLC cache size may be maintained (e.g., by decreasing reallocation of memory cells in the SLC cache to MLC storage). In contrast, in case of a heavier workload or an indication of memory overuse, more conservative GC operations are performed, and a smaller SW cache size can be maintained (e.g., by increasing reallocation of memory cells in the SLC cache to MW storage).) and perform, in accordance with the scheduling information, the one or more internal maintenance operations ([Liang 0024, 0075, 0088, Fig. 8] By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime. GC aggressiveness and/or SLC cache size may be adjusted in accordance with the wear-indicated device age or life expectancy. For example, in case of a lighter workload or an indication of memory underuse, more aggressive GC operations may be performed. At 830, a GC operation may be initiated or adjusted based at least on the wear-indicated device age or life expectancy. The GC process may be initiated during an idle state of the memory device (no active I/O access of the memory cells).).
Liang does not explicitly disclose transmit, to a host system, and receive, from the host system. Liang does disclose memory device communicating and receiving commands with a host ([Liang 0020-0021, 0026, 0032, 0067]).
Traister teaches transmit, to a host system, and receive, from the host system, ([Traister abstract, 0025-0026, 0028, Figs. 1A, 1B] The memory controller is configured to assign a priority level to one or more types of house keeping operations. Back end manager ("BEM") 150 comprises back end interface 146 and BE global scheduler 144. BE interface 146 serves to accommodate the particulars of memory 122 so that BE global scheduler ("BES") 144 can work with various different configurations/types of memory 122.BEM 150 in general, and BES 144 more specifically control the scheduling and servicing of operations required of memory 122. Data is sent/received by back end interface 146 over data bus 148, which may comprise all or some portion of buses 124 and 126 and control lines 142 of FIGS. 1A and 1B. A memory card according to the present invention will utilize time available between host commands to perform other operations. In prior systems, when an operation was taking place, the card would indicate that it was busy. However, as represented by step 204, in this embodiment, the card will indicate it is idle although it may be executing an operation in the background. A host command received in step 208 will be sent to the back end scheduler 144 in step 212. BES 144 will then, in step 216, compare the priority of the host command received in step 208 with the command or operation already being executed in the background, if any such operation is taking place.).
Liang and Traister are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Liang and Traister before him or her to modify the memory device of Liang to include the host scheduling of Traister, thereafter the memory device is connected to host scheduling. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device have more adaptive scheduling system where resources are allocated based on utilization of the memory as suggested by Traister. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Liang with Traister to obtain the invention as specified in the instant application claims.
With regards to non-exemplary limitations of claim 19, Liang teaches wherein the adjusted amount of work is adjusted from a size of the internal maintenance operations; ([Liang 0024] GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters.).
Referring to claim 2, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the one or more controllers are further configured to: determine a first amount of work based on a size of freed memory space associated with the internal maintenance operation work to be completed for the memory apparatus; ([Liang 0115, 0121] The GC controller can be configured to adjust an amount of memory space to be freed by a GC operation on a portion of the group of the memory cells according to the estimated wear-indicated device age relative to the tracked actual device age.) and determine a second amount of work based on the first amount of work and at least one of the one or more lifespan utilization parameters or the one or more types of additional maintenance operations, wherein the amount of internal maintenance operation work is based on the second amount of work ([Liang 0119] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes the GC controller that can be configured to adjust the amount of memory space to be freed by a GC operation using a comparison of the estimated wear-indicated device age to the actual device age.).
Referring to claim 3, Liang in view of Traister teaches
The memory apparatus of claim 2, wherein the one or more lifespan utilization parameters indicate that an actual utilization of the memory apparatus is ahead of estimated lifespan of the memory apparatus, and wherein the one or more controllers, to determine the second amount of work, are configured to: increase the first amount of work based on the one or more lifespan utilization parameters ([Liang 0092, 0094] Occurrence of a trigger even may trigger the GC tuning process (e.g., increase or decrease the GC), and/or memory cell allocation between SLC cache and MLC storage. In an example, the trigger event may include an actual device age exceeding an age threshold (e.g., 3 months from the first host write). Alternatively, the actual device age may be measured using actual cumulative P/E cycles, and the trigger event is the actual cumulative P/E cycles exceeding a P/E cycle threshold (e.g., 1000 P/E cycles). In another example, the trigger event may include a cumulative host write count N.sub.Host exceeding a byte count threshold, or a cumulative physical write count M.sub.NAND exceeds a byte count threshold. Using a trigger event to delay the invocation of GC process may improve system performance and user experience during an early age of the memory device.).
Referring to claim 4, Liang in view of Traister teaches
The memory apparatus of claim 2, wherein the one or more lifespan utilization parameters indicate that an actual utilization of the memory apparatus is behind an estimated lifespan of the memory apparatus, and wherein the one or more controllers, to determine the second amount of work, are configured to: decrease the first amount of work based on the one or more lifespan utilization parameters ([Liang 0092, 0121] In Example 7, the subject matter of any one or more of Examples 5-6 optionally includes the GC controller that can be configured to increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age by a specified margin, and withhold a GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age by a specified margin.).
Referring to claim 5, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the one or more lifespan utilization parameters indicate a write endurance utilization of the memory apparatus relative to an age of the memory apparatus ([Liang 0079-0081, 0083]The wear metric assessor 714 may use M.sub.NAND(t) to estimate a device wear metric ω(t), represented by a ratio of M.sub.NAND(t) to an SSD endurance. The SSD endurance is the total amount of data that can be written to the memory device (e.g., SSD), and can be measured as terabytes written (TBW), the total data amount that can be written to the physical media during device's lifespan. ).
Referring to claim 6, Liang in view of Traister teaches
The memory apparatus of claim 5, wherein the age of the memory apparatus is based on a real-time clock indication or an internal clock of the memory apparatus ([Liang 0056] The memory control unit 430 can control memory operations of the memory device 400 according to one or more signals or instructions received on control lines 432, including, for example, one or more clock signals or control signals that indicate a desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 416.).
Referring to claim 7, Liang in view of Traister teaches
The memory apparatus of claim 5, wherein the write endurance utilization is based on a comparison of a quantity of program-erase cycles performed by the memory apparatus to a cycle rating for the memory apparatus ([Liang 0009, 0073, 0092] The P/E cycles quantify an endurance of a flash device such as an SSD. Endurance may be expressed as a drive writes per day (DWPD), which measures how many times a host can overwrite the drive's entire size each day of its life. The device age may alternatively be measured by actual cumulative P/E cycles. The P/E cycle occurs whenever data is stored in flash memory. Maximum number of P/E cycles for the given flash architecture, known as flash cell endurance, is an indication of device life expectancy. The GC controller 616 may trigger the device age-adapted GC process if the actual cumulative P/E cycles exceed a P/E cycle threshold (e.g., approximately 1000 PE cycles in a non-limiting example).).
Referring to claim 8, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the one or more internal maintenance operations include at least one of: a defragmentation operation, a garbage collection operation, or a folding operation ([Liang abstract, 0020, 0030] adapting garbage collection (GC) operations in a memory device to an estimated device age. In some examples the string may be “folded,” and thus arranged relative to a U-shaped pillar. ).
Referring to claim 9, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the amount of internal maintenance operation work is an adjusted amount of work that is adjusted based on at least one of the one or more lifespan utilization parameters or the one or more types of additional maintenance operations ([Liang 0024] The present document describes examples of memory devices, systems, methods, and machine-readable mediums for adapting GC aggressiveness to a memory usage characteristic. According to some examples described herein, an adaptive GC engine may initiate or tune GC aggressiveness according to an estimated device age or life expectancy indicated by a current device wear metric. In this document, the GC aggressiveness refers to a size of memory space freed by the GC operations. A more aggressive GC therefore frees up more memory space than a less aggressive GC. The tuning (e.g., increasing or decreasing) of GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters. In various examples, tuning of GC aggressiveness may be based at least in part on a wear-indicated device age relative to an actual device age tracked over time and total writes over an expected lifetime of the memory device. The actual device age may be counted from a time of first use of the memory device (e.g., first memory write). For example, the adaptive GC engine can initiate or increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age, and withhold the GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.).
Referring to claim 10, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the scheduling information allocates time resources during which the memory apparatus is to perform the one or more internal maintenance operations, wherein the scheduling information includes an urgency rating, and wherein the one or more internal maintenance operations are determined based on the urgency rating ([Traister abstract, 0030-0032, Fig. 3A] The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. The card then executes the highest priority activity, which may not be the host command, as seen in step 224. For example a housekeeping command may be continued if that command has higher priority than the received command. The priority of the operations is delineated in Tables A and B below, reproduced as FIGS. 3A and 3B, respectively. Table A indicates at a high level the priority that will be associated with a general operation type. While in prior systems, a host command was generally serviced immediately (including any housekeeping operation required to properly service the command), in the present system, it has been determined that it is often more efficient to allow a housekeeping operation already being performed to be completed, and to service certain types of housekeeping commands prior to a host command, including housekeeping commands that are not needed or associated with particular host commands. Other housekeeping commands will have a lower priority, and thus a host command would have a higher priority than such a housekeeping command or operation.).
The same motivation that was utilized for combining Liang and Traister as set forth in claim(s) 1, 13, and 19 is equally applicable to this/these claim(s).
Referring to claim 11, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the amount of internal maintenance operation work includes at least one of: a size of the internal maintenance operation work, or an estimated amount of time for completion of the internal maintenance operation work ([Liang 0024] GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters.).
Referring to claim 12, Liang in view of Traister teaches
The memory apparatus of claim 1, wherein the one or more types of additional maintenance operations include at least one of: hot and cold data sorting, data sequentialization, a wear leveling operation, a table garbage collection operation, a table sequentialization operation, a data misalignment correction, or a zonification operation ([Liang 0022, 0033, 0083] Another approach is wear leveling, which involves evenly distributing P/E cycles to available cells to avoid overusing certain blocks. Persons skilled in the art will recognize that other forms of non-volatile memory may have analogous memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions. ).
Referring to claim 14, Liang in view of Traister teaches
The host system of claim 13, wherein the one or more controllers are further configured to: determine the scheduling information based on the amount of internal maintenance operation work and one or more operation parameters of the host system ([Liang 0024] The present document describes examples of memory devices, systems, methods, and machine-readable mediums for adapting GC aggressiveness to a memory usage characteristic. According to some examples described herein, an adaptive GC engine may initiate or tune GC aggressiveness according to an estimated device age or life expectancy indicated by a current device wear metric. In this document, the GC aggressiveness refers to a size of memory space freed by the GC operations. A more aggressive GC therefore frees up more memory space than a less aggressive GC. The tuning (e.g., increasing or decreasing) of GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters. In various examples, tuning of GC aggressiveness may be based at least in part on a wear-indicated device age relative to an actual device age tracked over time and total writes over an expected lifetime of the memory device. The actual device age may be counted from a time of first use of the memory device (e.g., first memory write). For example, the adaptive GC engine can initiate or increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age, and withhold the GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.).
Referring to claim 15, Liang in view of Traister teaches
The host system of claim 14, wherein the one or more operation parameters include at least one of: a charging state, a battery level, an activity level, or one or more applications executing on the host system ([Liang 0072] The GC controller 616 may initiate or adjust the GC operation based at least on the wear-indicated device age or life expectancy provided by the device age tracker circuit 614. The GC process may be initiated during an idle state of the memory device (e.g., no active I/O access of the memory cells like read or write commands for the host). ).
Referring to claim 16, Liang in view of Traister teaches
The host system of claim 13, wherein the one or more controllers are further configured to: receive, from the memory apparatus, an indication that the internal maintenance operations are to be performed by the memory apparatus; and transmit, to the memory apparatus, a request for the amount of work based on receiving the indication that the internal maintenance operations are to be performed by the memory apparatus, wherein the indication of the amount of internal maintenance operation work is received based on transmitting the request ([Liang abstract, 0024-0025, Figs. 8] adapting garbage collection (GC) operations in a memory device to an estimated device age. memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.).
Referring to claim 17, Liang in view of Traister teaches
The host system of claim 13, wherein the indication of the amount of internal maintenance operation work indicates a first amount of work, and wherein the scheduling information schedules the memory apparatus to perform a second amount of work that is based on the first amount of work and one or more operation parameters of the host system ([Liang 0092, 0121] In Example 7, the subject matter of any one or more of Examples 5-6 optionally includes the GC controller that can be configured to increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age by a specified margin, and withhold a GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age by a specified margin.).
Referring to claim 18, Liang in view of Traister teaches
The host system of claim 13, wherein the scheduling information includes an urgency rating ([Traister abstract, 0030-0032, Fig. 3A] The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. The card then executes the highest priority activity, which may not be the host command, as seen in step 224. For example a housekeeping command may be continued if that command has higher priority than the received command. The priority of the operations is delineated in Tables A and B below, reproduced as FIGS. 3A and 3B, respectively. Table A indicates at a high level the priority that will be associated with a general operation type. While in prior systems, a host command was generally serviced immediately (including any housekeeping operation required to properly service the command), in the present system, it has been determined that it is often more efficient to allow a housekeeping operation already being performed to be completed, and to service certain types of housekeeping commands prior to a host command, including housekeeping commands that are not needed or associated with particular host commands. Other housekeeping commands will have a lower priority, and thus a host command would have a higher priority than such a housekeeping command or operation.).
The same motivation that was utilized for combining Liang and Traister as set forth in claim(s) 1, 13, and 19 is equally applicable to this/these claim(s).
Referring to claim 20, Liang in view of Traister teaches
The method of claim 19, further comprising: adjusting the size of the internal maintenance operations to obtain the adjusted amount of work based on at least one of: one or more lifespan utilization parameters, or one or more types of additional maintenance operations ([Liang 0024] The present document describes examples of memory devices, systems, methods, and machine-readable mediums for adapting GC aggressiveness to a memory usage characteristic. According to some examples described herein, an adaptive GC engine may initiate or tune GC aggressiveness according to an estimated device age or life expectancy indicated by a current device wear metric. In this document, the GC aggressiveness refers to a size of memory space freed by the GC operations. A more aggressive GC therefore frees up more memory space than a less aggressive GC. The tuning (e.g., increasing or decreasing) of GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters. In various examples, tuning of GC aggressiveness may be based at least in part on a wear-indicated device age relative to an actual device age tracked over time and total writes over an expected lifetime of the memory device. The actual device age may be counted from a time of first use of the memory device (e.g., first memory write). For example, the adaptive GC engine can initiate or increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age, and withhold the GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.).
Referring to claim 21, Liang in view of Traister teaches
The method of claim 20, wherein the one or more lifespan utilization parameters indicate whether an actual utilization of the memory apparatus is behind or ahead of an estimated lifespan of the memory apparatus, and wherein adjusting the size of the internal maintenance operations comprises: adjusting the size of the internal maintenance operations based on whether the actual utilization of the memory apparatus is behind or ahead of the estimated lifespan ([Liang 0092, 0094, 0121] Occurrence of a trigger even may trigger the GC tuning process (e.g., increase or decrease the GC), and/or memory cell allocation between SLC cache and MLC storage. In an example, the trigger event may include an actual device age exceeding an age threshold (e.g., 3 months from the first host write). Alternatively, the actual device age may be measured using actual cumulative P/E cycles, and the trigger event is the actual cumulative P/E cycles exceeding a P/E cycle threshold (e.g., 1000 P/E cycles). In another example, the trigger event may include a cumulative host write count N.sub.Host exceeding a byte count threshold, or a cumulative physical write count M.sub.NAND exceeds a byte count threshold. Using a trigger event to delay the invocation of GC process may improve system performance and user experience during an early age of the memory device. In Example 7, the subject matter of any one or more of Examples 5-6 optionally includes the GC controller that can be configured to increase the amount of memory space to be freed by a GC operation if the actual device age exceeds the wear-indicated device age by a specified margin, and withhold a GC operation or decrease the amount of memory space to be freed by a GC operation if the actual device age is less than the wear-indicated device age by a specified margin.).
Referring to claim 22, Liang in view of Traister teaches
The method of claim 20, wherein the one or more types of additional maintenance operations include one or more optional internal maintenance operations, and wherein adjusting the size of the internal maintenance operations comprises: increasing the size of the internal maintenance operations based on the one or more types of additional maintenance operations including the one or more optional internal maintenance operations ([Liang 0092, 0094] Occurrence of a trigger even may trigger the GC tuning process (e.g., increase or decrease the GC), and/or memory cell allocation between SLC cache and MLC storage. In an example, the trigger event may include an actual device age exceeding an age threshold (e.g., 3 months from the first host write). Alternatively, the actual device age may be measured using actual cumulative P/E cycles, and the trigger event is the actual cumulative P/E cycles exceeding a P/E cycle threshold (e.g., 1000 P/E cycles). In another example, the trigger event may include a cumulative host write count N.sub.Host exceeding a byte count threshold, or a cumulative physical write count M.sub.NAND exceeds a byte count threshold. Using a trigger event to delay the invocation of GC process may improve system performance and user experience during an early age of the memory device.).
Referring to claim 23, Liang in view of Traister teaches
The method of claim 19, further comprising: receiving, from the host system, a request for an indication of an amount of work for the internal maintenance operations, wherein transmitting the indication of the adjusted amount of work is based on receiving the request ([Liang abstract, 0024-0025, Figs. 8] adapting garbage collection (GC) operations in a memory device to an estimated device age. memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. By addressing important issues of amount of GC to perform and when to initiate GC process, the adaptive GC described in this document can help improve a balance of user experience, device performance, and device lifetime.).
Referring to claim 24, Liang in view of Traister teaches
The method of claim 19, wherein the indication of the adjusted amount of work indicates a size of the adjusted amount of work or an estimated amount of time associated with the memory apparatus performing the adjusted amount of work ([Liang 0024] GC aggressiveness may include tuning one or more of GC speed, frequency, time duration, or a size of memory space (e.g., a number of erase blocks) targeted for GC operations, among other parameters.).
Referring to claim 25, Liang in view of Traister teaches
The method of claim 19, wherein the size of the internal maintenance operations is an estimated amount of memory space generated by performing the internal maintenance operations ([Liang 0115, 0121] The GC controller can be configured to adjust an amount of memory space to be freed by a GC operation on a portion of the group of the memory cells according to the estimated wear-indicated device age relative to the tracked actual device age.).
Conclusion
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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