Prosecution Insights
Last updated: August 17, 2026
Application No. 19/219,517

BOOTSTRAP CAPACITANCE CHARGING SCHEME FOR GALLIUM NITRIDE BASED BRIDGE DRIVER

Non-Final OA §112
Filed
May 27, 2025
Priority
Oct 11, 2024 — IN 202441077214 +1 more
Examiner
O NEILL, PATRICK
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
481 granted / 577 resolved
+15.4% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
14 currently pending
Career history
585
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
28.7%
-11.3% vs TC avg
§102
35.9%
-4.1% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 577 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in India on 10/22/2024. It is noted, however, that applicant has not filed a certified copy of the 202441077217 application as required by 37 CFR 1.55. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the wherein the second power supply is capable of charging the capacitor via the NMOS transistor and the pair of PMOS transistors at a higher voltage than the first power supply as claimed in claim 1; wherein the second power supply is capable of charging the capacitor via a NMOS transistor and a pair of PMOS transistors connected in series with the NMOS transistor as claimed in claim 14; and utilizing the second power supply to charge a capacitor connected between a bootstrap supply terminal (HB) and a switching terminal (HS) of a bridge driver via a NMOS transistor and a pair of PMOS transistors connected in series with the NMOS transistor as claimed in claim 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. a) regarding claims 1, 14 and 15: The limitations: “wherein the second power supply is capable of charging the capacitor via the NMOS transistor and the pair of PMOS transistors at a higher voltage than the first power supply,” of claim 1; “wherein the second power supply is capable of charging the capacitor via a NMOS transistor and a pair of PMOS transistors connected in series with the NMOS transistor,” of claim 14; and “utilizing the second power supply to charge a capacitor connected between a bootstrap supply terminal (HB) and a switching terminal (HS) of a bridge driver via a NMOS transistor and a pair of PMOS transistors connected in series with the NMOS transistor,” of claim 15 fail to comply with the written description requirement. Paragraph [0019] of the specification states, “The shared source terminal 206 of the pair of PMOS transistors 204_1 and 204_2 connects to a first power supply VDD at a first power supply terminal 209, wherein their shared drain terminal 207 connects in series to the source terminal of the NMOS transistor 202…The bootstrap capacitance charger 120 further comprises a charge pump 208 capable of generating a second/additional power supply VCP at a second power supply terminal 211, wherein the second power supply is utilized by a gate driver 210 to charge bootstrap capacitor 114 via the NMOS transistor 202 and the pair of PMOS transistors 204_1 and 204_2” The specification and Figure 2 disclose the bootstrap capacitor is charged by the first power supply VDD via transistors 204_1, 204_2 and 202. The second power supply VCP is utilized by the gate driver 210 to control charging of the bootstrap capacitor, however the second power supply VCP is not charging the bootstrap capacitor as claimed. a) regarding claims 2-13 and 16-22: The claims are rejected based on their dependence from claims 1 and 15, respectively. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fukushima (US 12,015,349) discloses a switching circuit that suppresses the overcharging of a bootstrap capacitor. Ptacek et al. (US 2024/0097555) discloses a driver that is suitable for use with a gallium nitride (GaN) power stage. Jodka et al. (US 11,196,339) discloses a charge pump for a gate driver. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick O'Neill whose telephone number is (571)270-1677. The examiner can normally be reached Monday- Friday 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571)270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK O NEILL/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

May 27, 2025
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+17.5%)
2y 0m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 577 resolved cases by this examiner. Grant probability derived from career allowance rate.

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