Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 07/03/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-17 of US Patent No.: 12,321,643. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the following reasons:
Claims 1-17 of US Patent No.: 12,321,643 (hereinafter, “Patent”), contains every element of claims 1-20 of the instant application (hereinafter, “Instant Applicant”) and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
“Claim 12 and Claim 13 are generic to the species of invention covered by claim 3 of the patent. Thus, the generic invention is "anticipated" by the species of the patented invention. Cf., Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (holding that an earlier species disclosure in the prior art defeats any generic claim) 4. This court's predecessor has held that, without a terminal disclaimer, the species claims preclude issuance of the generic application. In re Van Ornum, 686 F.2d 937, 944, 214 USPQ 761, 767 (CCPA 1982); Schneller, 397 F.2d at 354. Accordingly, absent a terminal disclaimer, claims 12 and 13 were properly rejected under the doctrine of obviousness-type double patenting.” (In re Goodman (CA FC) 29 USPQ2d 2010 (12/3/1993).
US Patent No.: 12,321,643
Instant Application
1. A method, comprising: receiving a series of commands at a memory device, wherein the series of commands comprises a command; determining an error associated with the command; accessing respective locations of a memory array of the memory device in response to the series of commands, wherein accessing at least one of the respective locations occurs concurrently with determining the error; and transmitting signaling to a host device that indicates the error associated with the command
1. A method, comprising: receiving a first command and a second command at a memory device; accessing a first location of a memory array of the memory device in response to the first command; and transmitting signaling to a host device associated with one or more errors that are detected in the second command, wherein accessing the first location occurs at least partially concurrently with transmitting the signaling to the host device.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 8 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 8 and 15 recite “wherein accessing the first location occurs at least partially concurrently with transmitting the signaling to the host device”.
The limitation of “wherein accessing the first location occurs at least concurrently with transmitting the signaling to the host device” is clearly disclosed by the applicant’s original disclosure.
However, the limitation of “wherein accessing the first location occurs at least partially concurrently with transmitting the signaling to the host device” is NOT disclosed by the applicant’s original disclosure.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-11, 14-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LOVELACE et al. (Pub. No.: US 2019/0034365).
Regarding independent claims 1, 8 and 15, LOVELACE discloses a method, comprising: receiving a first command and a second command at a memory device; accessing a first location of a memory array of the memory device in response to the first command; and transmitting signaling to a host device associated with one or more errors that are detected in the second command, wherein accessing the first location occurs at least partially concurrently with transmitting the signaling to the host device ([0097]: a memory module includes multiple dynamic random access memories (DRAMs), a register including logic to receive commands from a memory controller and transmit the commands to one or more DRAMs via the internal C/A signal lines of the memory module, the register to: receive a first command from the memory controller and transmit the first command to a DRAM with parity checking enabled, the first command to include valid parity and chip select asserted, receive commands in cycles before and after the first command, and transmit the commands to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted, and logic to, in response to detecting a parity error from the DRAM, signal the parity error to the memory controller, wherein the memory controller is to modify a timing parameter to adjust timing for the internal C/A signal lines of the memory module in response to the parity error).
Regarding claims 2, 9 and 16, LOVELACE teaches accessing a second location of the memory array in response to the second command (Fig.1).
Regarding claims 3, 10 and 17, LOVELACE teaches decoding the first command, wherein the first location is accessed based at least in part on decoding the first command (Fig.1).
Regarding claims 4, 11 and 18, LOVELACE teaches wherein transmitting the signaling comprises: setting a voltage of a pin to indicate the one or more errors ([0024]).
Regarding claims 7, 14 and 20, LOVELACE teaches wherein the memory device comprises a dynamic random access memory (DRAM), and wherein the first command and the second command are received at the DRAM ([0097]: the first command to include valid parity and chip select asserted, receive commands in cycles before and after the first command, and transmit the commands to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted).
Allowable Subject Matter
Claims 5, 6, 12, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 5, 12 and 19identify the distinct features “determining, based at least in part on the first command, an instruction for access of the memory array; and determining one or more second errors based at least in part on comparing a type of access for the first location to the instruction", which are not taught or suggested by the prior art of records.
Claim 6, 13 identify the distinct features “determining a matrix (MAT) or a sub-array of the memory array corresponding to the first location; and determining one or more second errors associated with the first command based at least in part on the MAT or the sub-array of the memory array", which are not taught or suggested by the prior art of records.
Claims 5, 6, 12, 13 and 19 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SEO et al. (Pub. No.: US 2015/0178224) “METHODS FOR OPERATING DATA STORAGE DEVICE CAPABLE OF DATA DE-DUPLICATION”
Considered for teachings related to data de-duplication technologies, and more particularly, to methods for operating a data storage device which is configured to perform a data de-duplication function, and to methods for operating a system including such a data storage device.
Does not disclose or suggest receiving a first command and a second command at a memory device; accessing a first location of a memory array of the memory device in response to the first command; and transmitting signaling to a host device associated with one or more errors that are detected in the second command, wherein accessing the first location occurs at least partially concurrently with transmitting the signaling to the host device.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PMR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-irect.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/YONG J CHOE/Primary Examiner, Art Unit 2135
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