DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 9th, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, 14-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Publication No. 2016/0188410 – “Lee”) in view of Fleming et al. (US Publication No. 2020/0327953 – “Fleming”) in further view of Jinzenji et al. (US Publication No. 2016/0321172 – “Jinzenji”).
Regarding claim 1, Lee teaches A system comprising: a memory device comprising a processing device, operatively coupled with the memory device, to perform operations comprising: (Lee paragraph [0110], The processor 101A may include a circuit, interfaces, or a program code for processing data and controlling operations of the components of the storage system 2000A. For example, the processor 101A may include a central processing unit (CPU), an advanced risk machine (ARM) processor, or an application specific integrated circuit (ASIC) obtaining, using a fill threshold index (FTI) data structure and the LUN, a block stripe of the LU identified by the LUN, (Lee paragraph [0098], Accordingly, the RAM 1500 may store the mapping table information. The mapping table information may include an address mapping table which converts a logical address to a physical address, and a stripe mapping table which represents information about stripe grouping. The stripe mapping table may include valid page ratio information of each stripe. Block stripes can be obtained based on page fill ratio information) selecting, using a mapping data structure and an identifier of the block stripe, a particular memory block of the block stripe within the LUN; (Lee paragraph [0098], Accordingly, the RAM 1500 may store the mapping table information. The mapping table information may include an address mapping table which converts a logical address to a physical address, and a stripe mapping table which represents information about stripe grouping. The stripe mapping table may include valid page ratio information of each stripe. Mapping structures and identifiers (i.e., address information) may be used to select a block stripe).
Lee does not teach a plurality of memory die, each memory die comprising a plurality of memory blocks; identifying a memory block candidate of the plurality of memory blocks within a logical unit (LU), wherein the LU is identified by a logical unit number (LUN); wherein the block stripe is associated with a highest FTI value; and performing a memory scan operation on the particular memory block.
However, Fleming teaches a plurality of memory die, each memory die comprising a plurality of memory blocks; (Fleming paragraph [0089], The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. The memory device may include a plurality of memory dies, which can include a plurality of memory blocks, as is typical in flash memory, see Fleming paragraph [0031], In some implementations, the storage array controllers 110A-D may be configured for offloading device management responsibilities from storage drive 171A-F in storage array 102A-B. For example, storage array controllers 110A-D may manage control information that may describe the state of one or more memory blocks in the storage drives 171A-F) identifying a memory block candidate of the plurality of memory blocks within a logical unit (LU), wherein the LU is identified by a logical unit number (LUN); (Fleming paragraph [0022], A storage system described herein tracks flash memory (or other solid-state storage memory), using an adaptive bad blocks threshold. When the amount of bad blocks in a plane or LUN (logical unit number) of flash memory meets the bad blocks threshold, the storage system records the plane or LUN as bad. The storage system adjusts the bad blocks threshold for the flash memory, in some embodiments separately for each individual flash drive, storage node or storage unit, and in further embodiments separately for each type of flash memory. In various combinations, storage system embodiments use linear or other interpolation for the bad blocks threshold, a cap or maximum value of bad blocks threshold, weighted or adjustable weighted types of failures for comparison with the bad blocks threshold, and/or write control to a plane undergoing block testing as features in tracking flash or other solid-state memory, as described with reference to FIGS. 4-8. A memory block of a LU may be selected based on criteria, such as bad block threshold stats) and performing a memory scan operation on the particular memory block (Fleming paragraph [0032], The instructions may be executed by a controller (not shown) associated with or otherwise located on the storage drive 171A-F and may cause the storage drive 171A-F to scan a portion of each memory block to identify the memory blocks that store control information for the storage drives 171A-F. The storage drives 171A-F may respond by sending a response message to the storage array controller 110A-D that includes the location of control information for the storage drive 171A-F. Responsive to receiving the response message, storage array controllers 110A-D may issue a request to read data stored at the address associated with the location of control information for the storage drives 171A-F. Fleming teaches performing a memory scan on a selected memory block).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee with those of Fleming. Fleming teaches a memory structure including a plurality of dies and memory blocks, as well as structured logical units, which can also be used to identify and perform memory scans, which enables more accurate locating and detection of issues that may arise with the memory device (i.e., see Fleming paragraph [0032], In implementations, storage array controllers 110A-D may offload device management responsibilities from storage drives 171A-F of storage array 102A-B by retrieving, from the storage drives 171A-F, control information describing the state of one or more memory blocks in the storage drives 171A-F. Retrieving the control information from the storage drives 171A-F may be carried out, for example, by the storage array controller 110A-D querying the storage drives 171A-F for the location of control information for a particular storage drive 171A-F. The storage drives 171A-F may be configured to execute instructions that enable the storage drive 171A-F to identify the location of the control information. The instructions may be executed by a controller (not shown) associated with or otherwise located on the storage drive 171A-F and may cause the storage drive 171A-F to scan a portion of each memory block to identify the memory blocks that store control information for the storage drives 171A-F. The storage drives 171A-F may respond by sending a response message to the storage array controller 110A-D that includes the location of control information for the storage drive 171A-F. Responsive to receiving the response message, storage array controllers 110A-D may issue a request to read data stored at the address associated with the location of control information for the storage drives 171A-F).
Lee in view of Fleming does not teach wherein the block stripe is associated with a highest FTI value.
However, Jinzenji teaches wherein the block stripe is associated with a highest FTI value (Jinzenji paragraph [0077], For example, as shown in FIG. 8, if valid data VD12 in the block BK12 is written in block BK00 to which data are to be transferred, the number of processed blocks during the garbage collection is two. Thus, in this case, the memory controller 20 determines that the number of processed blocks is not less than or equal to the threshold value (No in S24), and switches the block list from which block to be subjected to the garbage collection is selected, from the first block list L1 to the second block list L2. The memory controller 20 selects the block BK21 with the greatest valid data ratio from the second block list L2 as a block to be subjected to the garbage collection. Upon receiving a garbage collection operation, the blocks may be searched from a list to find the block with the greatest page fill information for selection).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee and Fleming with those of Jinzenji. Jinzenji teaches using the amount of valid data, as well as the ratio of valid data, of a block as a means to select a block for a variety of operations. Selecting a block with the greatest ratio of valid data allows for more flexibility regarding a data transfer operation, such as allowing for a much larger amount of data transfer for data units of a predetermined size (i.e., see Jinzenji paragraph [0088], For example, to reduce the write times TGCW1 and TGCW2, a block with many valid data VD (block with a high valid data ratio) needs to be selected as a block from which data is transferred. The block with many valid data VD includes many valid data VD that can be transferred. Thus, the data size of the valid data VD that is to be transferred from the block amounts to a write unit (for example, page size). Accordingly, the write times TGCW1 and TGCW2 required for the garbage collection depend on the time to fill a predetermined data size (for example, page size) with the data to be transferred).
Claims 8 and 15 are the corresponding method and non-transitory computer readable medium claims to system claim 1. They are rejected with the same references and rationale.
Regarding claim 2, Lee in view of Fleming in further view of Jinzenji teaches The system of claim 1, wherein the FTI data structure stores an FTI value for each block stripe grouped by the LUNs (Lee paragraph [0098], Accordingly, the RAM 1500 may store the mapping table information. The mapping table information may include an address mapping table which converts a logical address to a physical address, and a stripe mapping table which represents information about stripe grouping. The stripe mapping table may include valid page ratio information of each stripe. The FTI data structure (i.e., RAM) stores FTI (i.e., valid page ratio information) for each block stripe, which can be grouped according to logical address information).
Claims 9 and 16 are the corresponding method and non-transitory computer readable medium claims to system claim 2. They are rejected with the same references and rationale.
Regarding claim 3, Lee in view of Fleming in further view of Jinzenji teaches The system of claim 1, wherein the block stripe associated with the highest FTI value is obtained by iterating through the FTI data structure for the LUN to identify the block stripe that has the highest FTI value as the block stripe with a highest page fill (Jinzenji paragraph [0077], For example, as shown in FIG. 8, if valid data VD12 in the block BK12 is written in block BK00 to which data are to be transferred, the number of processed blocks during the garbage collection is two. Thus, in this case, the memory controller 20 determines that the number of processed blocks is not less than or equal to the threshold value (No in S24), and switches the block list from which block to be subjected to the garbage collection is selected, from the first block list L1 to the second block list L2. The memory controller 20 selects the block BK21 with the greatest valid data ratio from the second block list L2 as a block to be subjected to the garbage collection. Upon receiving a garbage collection operation, the blocks may be searched from a list to find the block with the greatest page fill information for selection).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee and Fleming with those of Jinzenji. Jinzenji teaches using the amount of valid data, as well as the ratio of valid data, of a block as a means to select a block for a variety of operations. Selecting a block with the greatest ratio of valid data allows for more flexibility regarding a data transfer operation, such as allowing for a much larger amount of data transfer for data units of a predetermined size (i.e., see Jinzenji paragraph [0088], For example, to reduce the write times TGCW1 and TGCW2, a block with many valid data VD (block with a high valid data ratio) needs to be selected as a block from which data is transferred. The block with many valid data VD includes many valid data VD that can be transferred. Thus, the data size of the valid data VD that is to be transferred from the block amounts to a write unit (for example, page size). Accordingly, the write times TGCW1 and TGCW2 required for the garbage collection depend on the time to fill a predetermined data size (for example, page size) with the data to be transferred).
Claims 10 is the corresponding method claim to system claim 3. It is rejected with the same references and rationale.
Regarding claim 7, Lee in view of Fleming in further view of Jinzenji teaches The system of claim 1, wherein the memory scan operation comprises at least one of a read level calibration scan, a data retention scan, or a bit error scan (Lee paragraph [0079], The memory 144 can store data necessary for performing operations such as data writing and data reading requested by the host 102 and/or data transfer between the memory device 150 and the controller 130 for background operations such as garbage collection and wear levelling as described above. In accordance with an embodiment, for supporting operations in the memory system 110, the memory 144 may include a program memory, a data memory, a write buffer/cache, a read buffer/cache, a data buffer/cache, a map buffer/cache, and the like. Lee can perform the memory operations as a background memory operation, including the aforementioned memory scan and data retention, see Lee paragraph [0172], Referring to FIG. 12, memory system may select a victim block for garbage collection operation at step 91. The garbage collection operation is generally performed in a background operation in which the memory system does not process commands entered from the host. The garbage collection operation may not be performed in a free block among plural blocks in the memory device, nor in an open block in which data is programmed. The garbage collection operation can be performed by preferentially selecting a block having a low percentage of valid data among the blocks which are in a closed state. According to an embodiment, a victim block may be first selected based on data retention, instead of a ratio of valid data stored in the block, among the plural blocks which are in a closed state).
Claims 14 and 20 are the corresponding method and non-transitory computer readable medium claims to system claim 7. They are rejected with the same references and rationale.
Claim(s) 4-6, 11-13 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Fleming in further view of Jinzenji as applied to claims 1, 8 and 15 above, and further in view of Byun (US Publication No. 2020/0387447 – “Byun”).
Regarding claim 4, Lee in view of Fleming in further view of Jinzenji and further in view of Byun teaches The system of claim 1, further comprising updating a FTI value of a particular block stripe in the FTI data structure by: (see Lee for FTI data structure) determining a page number for a page write; (Byun paragraph [0034], By way of example but not limitation, the host request manager 46 may use the map manager 44 and the block manager 48 to handle or process requests according to the read and program commands, and events which are delivered from the host interface 132. The host request manager 46 may send an inquiry request to the map manager 44, to determine a physical address corresponding to the logical address which is entered with the events. The host request manager 46 may send a read request with the physical address to the memory interface 142, to process the read request (or handle the events). On the other hand, the host request manager 46 may send a program request (or write request) to the block manager 48, to program entered data to a specific page of the unrecorded (no data) in the memory device 150. Then, the host request manager 46 may transmit a map update request corresponding to the program request to the map manager 44, to update an item relevant to the program med data in information of mapping the logical-to-physical addresses to each other. A specific page may be selected for a write operation) determining, using a page threshold table, (see Jinzenji below for page threshold table) a corresponding FTI value based on the page number; (Byun paragraph [0036], The block manager 48 may be configured to manage blocks in the memory device 150 according to the number of valid pages. Further, the block manager 48 may select and erase blocks having no valid pages when a free block is needed, and select a block including the least valid page when it is determined that garbage collection is necessary. The state manager 42 may perform garbage collection to move the valid data to an empty block and erase the blocks containing the moved valid data so that the block manager 48 may have enough free blocks (i.e., empty blocks with no data). If the block manager 48 provides information regarding a block to be erased to the state manager 42, the state manager 42 may check all flash pages of the block to be erased to determine whether each page is valid. For example, to determine validity of each page, the state manager 42 may identify a logical address stored in an area (e.g., an out-of-band (OOB) area) of each page. To determine whether each page is valid, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the inquiry request. The state manager 42 sends a program request to the block manager 48 for each valid page. A mapping table may be updated through the update of the map manager 44 when the program operation is completed. The page for the targeted write operation may have the valid page index determined by a block manager, which will update mapping metadata regarding the new index count value) and updating the FTI value of the particular block stripe in the FTI data structure based on the FTI value determined using the page threshold table (Jinzenji paragraph [0056], Here, the structures of the first and second block lists L1 and L2 are not limited to those shown in FIGS. 4A and 4B. For example, the number of valid data units may be used instead of the valid data ratio. Moreover, the valid data ratio is unnecessary if a corresponding valid data ratio can be referred to using a block number. For example, if a table indicating the number of valid data (number of valid clusters) of all the blocks 31 is provided, the number of valid data of a block can be determined from the block number by causing the memory controller 20 to refer to the table. Thus, in such a case, the valid data ratio is unnecessary in the first and second block lists L1 and L2. It suffices that only the block numbers arranged in the same manner on the basis of the valid data ratio are indicated. The valid data ratio fill index may be determined and updated using the page threshold table).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee, Fleming and Jinzenji with those of Byun. Byun teaches using page data for certain operations such as page writes or updating fill information data, which can allow for more specific targeting of particular pages, rather than using the broader block/block stripe data (i.e., see Byun paragraph [0034], The host request manager 46 may send an inquiry request to the map manager 44, to determine a physical address corresponding to the logical address which is entered with the events. The host request manager 46 may send a read request with the physical address to the memory interface 142, to process the read request (or handle the events). On the other hand, the host request manager 46 may send a program request (or write request) to the block manager 48, to program entered data to a specific page of the unrecorded (no data) in the memory device 150. Then, the host request manager 46 may transmit a map update request corresponding to the program request to the map manager 44, to update an item relevant to the program med data in information of mapping the logical-to-physical addresses to each other and paragraph [0036], Further, the block manager 48 may select and erase blocks having no valid pages when a free block is needed, and select a block including the least valid page when it is determined that garbage collection is necessary. The state manager 42 may perform garbage collection to move the valid data to an empty block and erase the blocks containing the moved valid data so that the block manager 48 may have enough free blocks (i.e., empty blocks with no data). If the block manager 48 provides information regarding a block to be erased to the state manager 42, the state manager 42 may check all flash pages of the block to be erased to determine whether each page is valid).
Claims 11 and 17 are the corresponding method and non-transitory computer readable medium claims to system claim 4. They are rejected with the same references and rationale.
Regarding claim 5, Lee in view of Fleming in further view of Jinzenji and further in view of Byun teaches The system of claim 4, wherein FTI values for each block stripe is stored contiguously in the FTI data structure (Byun paragraph [0088], First, a case where the threshold value TH is set as the valid page ratio is described. The victim block detector 1961B may detect, as the victim block, a closed block having a valid page ratio or less among the plurality of closed blocks included in the remaining dies. For example, the following description is given on the assumption that each memory block includes 100 pages. The victim block detector 1961B may select, as the victim block, a closed block having a valid page count of 25% or less, which is the valid page ratio, among the plurality of closed blocks. The valid page ratio may be set to any suitable value based on system conditions and performance objectives. The FTI values for a given block stripe (i.e., superblock) may be stored contiguously, such as in Byun Fig. 2; see Ref #A2 and #B2, as well as paragraph [0036], The block manager 48 may be configured to manage blocks in the memory device 150 according to the number of valid pages. Further, the block manager 48 may select and erase blocks having no valid pages when a free block is needed, and select a block including the least valid page when it is determined that garbage collection is necessary. The state manager 42 may perform garbage collection to move the valid data to an empty block and erase the blocks containing the moved valid data so that the block manager 48 may have enough free blocks (i.e., empty blocks with no data). If the block manager 48 provides information regarding a block to be erased to the state manager 42, the state manager 42 may check all flash pages of the block to be erased to determine whether each page is valid. For example, to determine validity of each page, the state manager 42 may identify a logical address stored in an area (e.g., an out-of-band (OOB) area) of each page).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee, Fleming and Jinzenji with those of Byun. Byun teaches using page data for certain operations such as page writes or updating fill information data, which can allow for more specific targeting of particular pages, rather than using the broader block/block stripe data (i.e., see Byun paragraph [0034], The host request manager 46 may send an inquiry request to the map manager 44, to determine a physical address corresponding to the logical address which is entered with the events. The host request manager 46 may send a read request with the physical address to the memory interface 142, to process the read request (or handle the events). On the other hand, the host request manager 46 may send a program request (or write request) to the block manager 48, to program entered data to a specific page of the unrecorded (no data) in the memory device 150. Then, the host request manager 46 may transmit a map update request corresponding to the program request to the map manager 44, to update an item relevant to the program med data in information of mapping the logical-to-physical addresses to each other and paragraph [0036], Further, the block manager 48 may select and erase blocks having no valid pages when a free block is needed, and select a block including the least valid page when it is determined that garbage collection is necessary. The state manager 42 may perform garbage collection to move the valid data to an empty block and erase the blocks containing the moved valid data so that the block manager 48 may have enough free blocks (i.e., empty blocks with no data). If the block manager 48 provides information regarding a block to be erased to the state manager 42, the state manager 42 may check all flash pages of the block to be erased to determine whether each page is valid).
Claims 12 and 18 are the corresponding method and non-transitory computer readable medium claims to system claim 5. They are rejected with the same references and rationale.
Regarding claim 6, Lee in view of Fleming in further view of Jinzenji and further in view of Byun teaches The system of claim 5, wherein the FTI value for each block stripe is determined (Lee paragraph [0098], Accordingly, the RAM 1500 may store the mapping table information. The mapping table information may include an address mapping table which converts a logical address to a physical address, and a stripe mapping table which represents information about stripe grouping. The stripe mapping table may include valid page ratio information of each stripe. Block stripes can be obtained based on page fill ratio information) via a direct memory access (DMA) engine (Fleming paragraph [0089], In the embodiment shown, the non-volatile solid state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (‘PLD’) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222. A DMA engine (i.e., DMA unit) may be utilized for controlling the flash memory, including blocks and dies).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee with those of Fleming, Jinzenji and Byun. Fleming teaches using a direct memory access unit which can allow for more efficient and reliable data transfer (i.e., see Fleming paragraph [0089], In some embodiments, energy reserve 218 is a capacitor, super-capacitor, battery, or other device, that supplies a suitable supply of energy sufficient to enable the transfer of the contents of DRAM 216 to a stable storage medium in the case of power loss. The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. In the embodiment shown, the non-volatile solid state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (‘PLD’) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222).
Claims 13 and 19 are the corresponding method and non-transitory computer readable medium claims to system claim 6. They are rejected with the same references and rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Koch et al. (US Publication No. 2021/0165576 – “Koch”) teaches a similar method of performing background operations, where the amount of valid data in a block stripe may be compared to a threshold value in order to determine whether to perform said operations, such as garbage collection (see Koch paragraph [0050], Greedy Garbage Collection: A greedy garbage collection method always chooses the least-valid block stripe in the system to garbage collect. One example method is implemented within the model using the following rules. When remaining media falls below a threshold, the least-valid block stripe is chosen to be a garbage collection ‘victim’, and all of the valid data is written to a new block stripe, freeing the blocks in the stripe to be erased and rewritten. As invalid locations are encountered in the victim stripe, new LBAs coming from the host are accepted and written. Since the victim stripe could contain many invalid locations, multiple victims can contribute data to a single destination block stripe).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached Monday - Friday 8 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached on (571)-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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