DETAILED ACTION
This office action is in response to application 19/221,050 filed 5/28/2025 that claims priority to provisional application 63/659,452 filed 6/13/2024 by Micron Technology, Inc.
Claims 1-22 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-14, 16, 18-19, and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (WO 2022/193143 A1)).
Regarding claim 1, Wang teaches A memory system, comprising: one or more memory devices; (Wang Fig. 1 and [0017] that discloses Memory System 110 containing Memory Devices 130-a and 130-b.) and processing circuitry coupled with the one or more memory devices (Wang Fig. 1 and [0019] that discloses Memory System Controller 115 coupled to Memory Devices 130-a and 130-b that receives requests from a host and converts the commands into instructions appropriate for the target memory device perform operations such as reading data, writing data. Wang [0021] discloses the memory system controller 155 may be circuitry. Thus the memory controller is an example of processing circuitry.) and configured to cause the memory system to: (Wang [0022] discloses the memory controller is executing stored operating code (i.e. executable code) that configures the controller to perform the operations.)
transfer data from a first zone of the memory system to a second zone of the memory system, (Consistent with para [0011] of the instant application a zone may be one or more blocks made up of pages. Wang [0031]-[0034] discloses during garbage collection data from one block is copied (i.e. transferred) to another block, thus is transferring data from a first zone to a second zone.) the memory system comprising a plurality of zones including the first zone and the second zone; (Wang [0026] discloses the system is composed of a set of blocks 170, thus there may be a first block and a second block.)
modify a mapping table to include information associated with an entry of a change log generated by transferring the data from the first zone to the second zone, (Wang [0031]-[0034] discloses when garbage collection is performed the system will track the changes in a validity mapping that indicates if the data stored at the corresponding page is valid (and may contain a logical block address and a physical address for the data) and update the validity data in a change log. Wang [0022] discloses the local memory 120 may function as a temporary cache for the change log data on the disk, and the cached copy may be a mapping table associated with an entry of the change log.)
wherein the information in the mapping table comprises a compressed version of one or more entries of the change log; (Consistent with para [0048] of the instant application, a compressed change log is a change log that uses less space than an uncompressed change log. Wang [0011] discloses that when the write is for a set of consecutive addresses, the change log will flag the entry as relating to a set of consecutive addresses. Thus Wang will not use a separate change log entry for each address, and the change log uses less space than in a system that has one entry per address, and the change log of Wang is a compressed change log and the mapping table that is a cache copy of the change log is a compressed version of the one or more entries of the change log.)
perform, based at least in part on modifying the mapping table, a read scan procedure to identify whether a program failure has occurred as part of transferring the data from the first zone to the second zone; (Consistent with paras [0011] and [0047] of the instant application a read scan procedure is a maintenance procedure that causes the system to read data. Thus garbage collection is an example of a read scan procedure. Wang [0033] discloses it will copy the data when performing the zone transfer, thus reads the data during a maintenance operation. Wang [0020] discloses the system may perform error-detecting and error-correction operations. Thus when Wang reads the data to copy it, Wang will perform error-detection and correction on the data read in the garbage collection process to insure that the newly copied data is correct.) and
perform, based at least in part on identifying that the program failure has occurred, an error handling procedure to recover the data using the mapping table. (Wang [0031]-[0034] discloses it will copy the data when performing the zone transfer, thus reads the data. Wang [0020] discloses the system may perform error-detecting and error-correction operations. Thus when Wang reads the data to copy, Wang will perform error-detection and correction on the data read in the garbage collection process)
Regarding claim 2, Wang teaches all the limitations of claim 1 above. Wang further teaches Wang further teaches wherein, to perform the error handling procedure, the processing circuitry is configured to cause the memory system to: determine a physical page address (PPA) of the first zone that stores the data using the mapping table; (Wang [0033] discloses during the garbage collection processes the system will identify any pages marked as valid, and copying the valid data from the source pages 175 to the new locations (one or more of the free pages 175 in another block) and to read the data, the system will determine the physical page address that stores the valid data using the compressed change log entry.) and perform a synchronization read operation to recover the data based at least in part on determining the PPA of the first zone. (Consistent with para [0011] and [0046] of the instant application, the system may perform a read as a management task such as error correction, and defragmentation. Garbage collection is an example of a management operation. Wang [0033] discloses performing garbage collection by reading the data to move to a new block (an example of a synchronization read operation) and would perform error detection on any data read to recover data based on the physical page address (PPA) of the data in the first zone. Wang [0022] discloses the mapping information from the change log will be loaded into cache (i.e. into the mapping table) to expedite the process.)
Regarding claim 4, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the processing circuitry is further configured to cause the memory system to: update, based at least in part on recovering the data, a logical-to-physical (L2P) table using the compressed version of the one or more entries of the change log included in the mapping table. (Wang [0031] discloses the system will update the change log for the newly copied data when performing garbage collection. Wang [0034] discloses the change log may contain both a logical and physical address. Wang [0022] discloses the local memory 120 may function as a temporary cache and will contain a copy of the data from the disk in order to relocate the block, thus the system may updated change log entries in the cache then write the updated data to the change log.)
Regarding claim 6, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the processing circuitry is further configured to cause the memory system to: release a virtual block of the first zone associated with the data after transferring the data to the second zone and based at least in part on modifying the mapping table. (Examiner notes that a virtual block may be a block associated with a logical address. Wang [0033] discloses that following the movement of the data from the source to the target, the system erases the source block (that is associated with a virtual address, and thus is a virtual block) and makes it available to store subsequent data (i.e. release the bock that was managed as a virtual block in a virtual to physical mapping).)
Regarding claim 7, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the processing circuitry is further configured to cause the memory system to: update the one or more entries in the change log based at least in part on transferring the data from the first zone to the second zone, wherein modifying the mapping table is in response to updating the one or more entries in the change log. (Wang [0033] discloses marking the data in the previously selected pages 175 as invalid, thus is updating the source and target entries in the compressed change log and its associated cache entries (i.e. the mapping table).)
Regarding claim 8, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein, to transfer the data, the processing circuitry is configured to cause the memory system to: transfer a first portion of the data to a first address of the second zone; update, based at least in part on transferring the first portion of the data, a first entry in the change log; (Wang [0033] discloses marking the data in the previously selected pages 175 as invalid, thus is updating the L2P table in the compressed change log and modifying the change log to show the newly created block is valid.)
transfer a second portion of the data to a second address of the second zone; (Wang [0033] discloses the system may transfer a plurality of pages, thus a second valid page that is copied is an example of transferring a second portion of the data to a second address of the second zone.) and update, based at least in part on transferring the second portion of the data, a second entry in the change log, (Wang [0047] discloses when consecutive data is copied the system will update the valid field for the second page in the change log, thus will update a second entry of the change log once the second page has successfully been copied.)
wherein modifying the mapping table is based at least in part on updating the first entry and the second entry in the change log. (Wang [0033] and [0047] discloses updating a first entry in the change log to show the source block is now invalid, and updating a second entry in the change log to show the new entry has valid data. Wang [0022] discloses the data in the mapping table that is a cached version of the change log will be updated as well.)
Regarding claim 9, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the change log comprises one or more entries indicating logical to physical (L2P) address mappings associated with the data. (Wang [0034] discloses the validity mapping that makes up the change log may contain both a logical block address (LBA) and a physical address)
Regarding claim 10, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the mapping table is stored in a buffer of the memory system. (Wang [0022] discloses the system may include local memory 120 that may serve as a cache for the memory controller and store in the local memory 120 data read from the memory device 130, such as one or more entries of the change log stored on the disks, and local memory 120 used to cache the data is an example of a buffer of the local memory 120.)
Regarding claim 11, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein transferring the data from the first zone to the second zone uses one or more write cursors. (examiner notes that consistent with para [0011] of the instant application a write cursor may be an address pointer and further notes a physical address is an example of an address pointer. Wang [0041] discloses when the system performs a write command it does so using one or more physical addresses, thus uses a physical address pointer (i.e. a cursor).)
Regarding claim 12, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein each zone of the plurality of zones comprises one or more pages of memory cells configured to be written sequentially (Wang [0035] discloses the system may receive and write consecutive (i.e. sequential) data.) and configured to be read in any order. (Wang [0030] discloses that each page may be programmed independently (i.e. in any order).)
Regarding claim 13, Wang teaches A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors of a memory system to cause the memory system to: (Wang [0036] teaches the memory system 130 may include non-transitory computer readable media storing instructions for performing the functions by the memory system controller 115. Wang [0021] discloses the memory system controller 155 may be circuitry which includes a processing circuitry.)
The remainder of claim 13 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 14 Wang teaches all of the limitation of claim 13 above.
The remainder of claim 13 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 16, Wang teaches all of the limitation of claim 13 above.
The remainder of claim 16 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 18, Wang teaches A method at a memory system, comprising: (Wang [Abstract] discloses the inventive concepts are directed towards a method of operating a memory device (i.e. memory system).)
The remainder of claim 13 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of clam 1 above.
Regarding claim 19, Wang teaches all of the limitation of claim 18 above.
The remainder of claim 19 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 21, Wang teaches all of the limitation of claim 18 above.
The remainder of claim 21 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 15, 17, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (WO 2022/193143 A1)) as detailed in claims 1, 13, and 18 above and further in view of Kim (KIM et al., US 2020/0310956 A1).
Regarding claim 3, Wang teaches all the limitations of claim 1 above. Wang further teaches wherein the processing circuitry is further configured to cause the memory system to: (Wang [0036] teaches the memory system 130 may include non-transitory computer readable media storing instructions for performing the functions by the memory system controller 115. Wang [0021] discloses the memory system controller 155 may be circuitry which includes a processing circuitry.)
However, wang does not explicitly disclose moving data in a garbage collection process based on a size of the data transfer, thus Wang does not explicitly teach determine whether to initiate the read scan procedure based at least in part on a size of the data transferred from the first zone to the second zone, wherein performing the read scan procedure is based at least in part on determining to initiate the read scan procedure.
Kim, of a similar field of endeavor, further teaches determine whether to initiate the read scan procedure based at least in part on a size of the data transferred from the first zone to the second zone, wherein performing the read scan procedure is based at least in part on determining to initiate the read scan procedure. (Kim [0006] and [0056] teaches that the system selects for garbage collections blocks that having a number of valid pages equal to or less than a predetermined number of pages in order to minimize the time spend in garbage collection. Kim [0047] discloses each page may correspond to a given size, for example 16 KB in the example of Fig. 4. Thus Kim determines whether to initiate garbage collection (an example of a read scan procedure) based on the size of the data to be transferred (the size of the valid data) from the source block (the first zone) to the destination block (the second zone).)
Wang and Kim are in a similar field of endeavor as both are related to storage systems that perform garbage collection. Thus it would have been obvious to a person of ordinary skill in the art before the effective filed date of the claimed invention to incorporate transferring garbage collections blocks to a new block only if the size of the data to transfer is at or below a threshold value. Thus combining prior art according to known methods to achieve predictable results (to minimize the garbage collection time, and leave the remainder of the time available for processing application I/O requests).)
Regarding claim 5, Wang teaches all the limitations of claim 1 above. However, Wang does not explicitly disclose wherein the processing circuitry is further configured to cause the memory system to: determine whether to transfer the data based at least in part on a quantity of the data stored in the first zone satisfying a threshold, wherein transferring the data is based at least in part on determining that the quantity satisfies the threshold.
Kim, of a similar field of endeavor, further discloses wherein the processing circuitry is further configured to cause the memory system to: determine whether to transfer the data based at least in part on a quantity of the data stored in the first zone satisfying a threshold, wherein transferring the data is based at least in part on determining that the quantity satisfies the threshold. (Kim [0006] and [0056] teaches that the system selects for garbage collections blocks that having a number of valid pages equal to or less than a predetermined number of pages in order to minimize the time spend in garbage collection. Kim [0047] discloses each page may correspond to a given size, for example 16 KB in the example of Fig. 4. Thus Kim determines whether to initiate garbage collection (an example of a read scan procedure) based on the size of the data to be transferred (the size of the valid data) from the source block (the first zone) to the destination block (the second zone).)
The motivation to combine Kim into the solution of Wang is the same as set forth in claim 3 above.
Regarding claim 15, Wang teaches all of the limitation of claim 13 above.
The remainder of claim 15 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 17, Wang teaches all of the limitation of claim 13 above.
The remainder of claim 17 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 20, Wang teaches all of the limitation of claim 18 above.
The remainder of claim 20 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 22, Wang teaches all of the limitation of claim 18 above.
The remainder of claim 22 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is:
Park (PARK 2019/0361804 A1). Park teaches that using a single entry for a plurality of sequential/consecutive mapping entries in a change log is an example of a compressed change log.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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