DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Drawings submitted on 5/28/2025 has been accepted by Examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2024-090291, filed on 06/03/2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 10, 14-17 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Yonemoto (US 20210314516 A1).
Regarding claim 1, Yonemoto discloses a photoelectric conversion device (fig. 4) comprising:
a plurality of pixels (21) including a first pixel and a second pixel (PX1-PX4, fig. 4),
wherein each of the plurality of pixels includes:
a first semiconductor layer (11a, fig. 1, The first substrate 11A includes a plurality of pixel blocks 21 each of which includes a plurality of pixels PX and a vertical scanning circuit 22. – ¶0064) including a photoelectric conversion unit (PD1-PD4, fig. 4), and a first readout circuit (MP1-MR4 + MA1-MA4, fig. 4) configured to read out a signal obtained based on photoelectric conversion by the photoelectric conversion unit (¶0094); and
a second semiconductor layer (11b and/or 11c, fig. 1) including a memory (41+42+43 and/or 51, fig. 4, ¶0075-0082) configured to hold a voltage corresponding to the signal, and an output circuit configured to output the voltage held in the memory (The third substrate 11C includes a plurality of ADC digital memory blocks 51 … ¶0078-0080), the first semiconductor layer and the second semiconductor layer being layered (fig. 1),
wherein the first readout circuit (MR1+MA1 in PX1, fig. 4) of the first pixel (PX1) includes a first amplification transistor (MA1, fig. 4),
wherein the first readout circuit (MP1+MA2, fig. 4) of the second pixel (PX2) includes a second amplification transistor (MA2, fig. 4),
wherein the first amplification transistor (MA1) is connected to a first current source (ML, fig. 4, …the load transistor ML functioning as a constant current source – ¶0070) via a first switch (MS1),
wherein the second amplification transistor (MA2, fig. 4) is connected to the first current source (ML) via a second switch (MS2, fig. 4), and
wherein the first amplification transistor (MA1) and the second amplification transistor (MA2) share the first current source (ML, evident from fig. 4).
Regarding claim 2, Yonemoto discloses the photoelectric conversion device according to claim 1, wherein the first current source is arranged in the second semiconductor layer (The second substrate 11B includes a plurality of ADC analog blocks 31 … , fig. 4, ¶0072).
Regarding claim 3, Yonemoto discloses the photoelectric conversion device according to claim 1,
wherein the plurality of pixels includes a third pixel (PX2, fig. 4) and a fourth pixel (PX4, fig. 4),
wherein the first readout circuit (MR3+MA3, fig. 4) of the third pixel (PX2) includes a third amplification transistor (MA3, fig. 4),
wherein the first readout circuit (MR4+MA4, fig. 4) of the fourth pixel (PX4) includes a fourth amplification transistor (MA4, fig. 4),
wherein the third amplification transistor (MA3, fig. 4) is connected to the first current source (ML, fig. 4) via a third switch (MS3),
wherein the fourth amplification transistor (MA4, fig. 4) is connected to the first current source (ML, fig. 4) via a fourth switch (MS4, fig. 4), and
wherein the first amplification transistor (MA1), the second amplification transistor (MA2), the third amplification transistor (MA3), and the fourth amplification transistor (MA4) share the first current source (ML, fig. 4; evident from fig. 4).
Regarding claim 4, Yonemoto discloses the photoelectric conversion device according to claim 1, further comprising:
a first joint portion (J1 in illustration 1 below) configured to electrically connect the first readout circuit (MR1+MA1) of the first pixel (PX1) and the memory (51, fig. 4, illustration 1); and
a second joint portion (J1 in illustration 1 below) configured to electrically connect the first readout circuit (MR2+MA2, fig. 4) of the second pixel (PX2) and the memory (51, fig. 4, illustration 1),
wherein the first current source is arranged between the first joint portion and the second joint portion in planar view (A plurality of MOS transistors TR is formed on the interface of the semiconductor substrate 131 on the side of the first substrate 11A (for example, substrate front surface side). The MOS transistors formed on the semiconductor substrate 131 includes, for example, the reset transistor MR, the amplification transistor MA, the select transistor MS, the load transistor ML, or the like. –¶0171, fig. 14. Also see illustration 2 below).
[AltContent: textbox (J1)]
[AltContent: arrow][AltContent: arrow][AltContent: textbox (J2)]
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Illustration – 1
[AltContent: textbox (second connection portion in a second wiring layer included in a second wiring structure)][AltContent: arrow][AltContent: textbox (First connection portion in a first wiring layer included in a first wiring structure)][AltContent: arrow][AltContent: textbox (TR, which implements ML is between J1 and J2, ¶0171)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (J2)][AltContent: textbox (J1)]
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Illustration-2
Regarding claim 5, Yonemoto discloses the photoelectric conversion device according to claim 1,
wherein the first pixel (PX1) and the second pixel (PX2) are provided with respective color filters (114, fig. 14, ¶0165), and
wherein the color filter provided on the first pixel and the color filter provided on the second pixel are filters with a same color (in Bayer Pattern, there are 2 Green color filters, ¶0165).
Regarding claim 6, Yonemoto discloses the photoelectric conversion device according to claim 1,
wherein the first pixel and the second pixel (PX1, PX2) are provided with respective color filters (114, fig. 14, ¶0165), and
wherein the color filter provided on the first pixel and the color filter provided on the second pixel are filters with different colors (in Bayer Pattern, has mixture of R, G, and B colors, ¶0165).
Regarding claim 7, Yonemoto discloses the photoelectric conversion device according to claim1, wherein the first switch is arranged in the first semiconductor layer (such implementation is possible according to fig. 3).
Regarding claim 10, Yonemoto discloses the photoelectric conversion device according to claim 1, wherein a third semiconductor layer (11c, fig. 1) including a second readout circuit (in this claim’s instance memory 62 function as second readout circuit, fig. 4) configured to read out the signal corresponding to the voltage held in the memory (in this claim’s instance, 41+42+43 function as memory, fig. 4, ¶0075-0084, ¶0135-0141) is further layered on the second semiconductor layer (third layer 11c is layered on the second semiconductor layer 11b, fig. 1).
Regarding claim 14, Yonemoto discloses the photoelectric conversion device according to claim 1, wherein the first switch and the second switch are arranged in the second semiconductor layer (evident for fig. 4).
Regarding claim 15, Yonemoto discloses the photoelectric conversion device according to claim 1, wherein the first switch and the second switch are arranged in the first semiconductor layer (supported and evident for fig. 3).
Regarding claim 16, Yonemoto discloses a photoelectric conversion system (camera 22, and/or system of figs. 23/24) comprising:
a photoelectric conversion device including a plurality of pixels including a first pixel and a second pixel,
wherein each of the plurality of pixels includes a first semiconductor layer including a photoelectric conversion unit, and a first readout circuit configured to read out a signal obtained based on photoelectric conversion by the photoelectric conversion unit; and a second semiconductor layer including a memory configured to hold a voltage corresponding to the signal, and an output circuit configured to output the voltage held in the memory, the first semiconductor layer and the second semiconductor layer being layered,
wherein the first readout circuit of the first pixel includes a first amplification transistor,
wherein the first readout circuit of the second pixel includes a second amplification transistor,
wherein the first amplification transistor is connected to a first current source via a first switch,
wherein the second amplification transistor is connected to the first current source via a second switch, and
wherein the first amplification transistor and the second amplification transistor share the first current source (see substantively equivalent claim 1 rejection above); and
a processing unit (12050, fig. 24) configured to generate an image using a signal output from the photoelectric conversion device (12031, fig. 24, ¶0229-0240).
Regarding claim 17, Yonemoto discloses a movable object (vehicle in fig. 25) comprising:
a photoelectric conversion device including a plurality of pixels including a first pixel and a second pixel,
wherein each of the plurality of pixels includes a first semiconductor layer including a photoelectric conversion unit, and a first readout circuit configured to read out a signal obtained based on photoelectric conversion by the photoelectric conversion unit; and a second semiconductor layer including a memory configured to hold a voltage corresponding to the signal, and an output circuit configured to output the voltage held in the memory, the first semiconductor layer and the second semiconductor layer being layered,
wherein the first readout circuit of the first pixel includes a first amplification transistor,
wherein the first readout circuit of the second pixel includes a second amplification transistor,
wherein the first amplification transistor is connected to a first current source via a first switch,
wherein the second amplification transistor is connected to the first current source via a second switch, and
wherein the first amplification transistor and the second amplification transistor share the first current source,
wherein the movable object includes a control unit configured to control movement of the movable object using a signal output from the photoelectric conversion device (see substantively equivalent claim 1 rejection above, ¶0240-0248).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yonemoto in view of Sakaguchi (US 20150341582 A1).
Regarding claim 8, Yonemoto discloses the photoelectric conversion device according to claim 1, except, wherein the first switch and the second switch operate in such a manner that when one of the first switch and the second switch is ON, the other is OFF.
Since in fig. 4, separate selection switches MS1-MS4 are used to read in signals from different pixels PX1-PX4, the control thereof using φs1- φs4, is envisioned to have different pulse characteristics (See fig. 4). Reading in also depends on shuttering mode, wherein the image capturing device can be operated in either local or global shuttering mode (¶0098). However, exact timing control characteristics is not found disclosed in Yonemoto.
However, in a comparable imaging device Sakaguchi discloses in fig. 3 a stacked semiconductor architecture, wherein signals from 4 pixels having 4 different PDs 201-204 are read in by pulsating φSEL1- φSEL4 (fig. 9), turning them ON and OFF at different times with respect to one another (fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the reading out operations of Yonemoto, using clocking scheme of Sakaguchi, so that selection switches are turned ON and OFF at different times with respect to one another, to obtain, wherein the first switch and the second switch operate in such a manner that when one of the first switch and the second switch is ON, the other is OFF, because, combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I).
Regarding claim 9, Yonemoto discloses the photoelectric conversion device according to claim 3, except, wherein the first switch, the secondswitch, the third switch,and the fourth switch operate in such a manner that when one of the first switch, the second switch, the third switch, and the fourth switch is ON, the remaining three switches are OFF.
Since in fig. 4, separate selection switches MS1-MS4 are used to read in signals from different pixels PX1-PX4, the control thereof using φs1- φs4, is envisioned to have different pulse characteristics (See fig. 4). Reading in also depends on shuttering mode, wherein the image capturing device can be operated in either local or global shuttering mode (¶0098). However, exact timing control characteristics is not found disclosed in Yonemoto.
However, in a comparable imaging device Sakaguchi discloses in fig. 3 a stacked semiconductor architecture, wherein signals from 4 pixels having 4 different PDs 201-204 are read in by pulsating φSEL1- φSEL4 (fig. 9), turning them ON and OFF at different times with respect to one another (fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the reading out operations of Yonemoto, using clocking scheme of Sakaguchi, so that selection switches are turned ON and OFF at different times with respect to one another, to obtain, wherein the first switch, the secondswitch, the third switch,and the fourth switch operate in such a manner that when one of the first switch, the second switch, the third switch, and the fourth switch is ON, the remaining three switches are OFF, because, combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I).
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yonemoto in view of Miyake (US 20250350859 A1).
Regarding claim 11, Yonemoto discloses the photoelectric conversion device according to claim 4, further comprising:
wherein the first joint portion is configured by joining a first connection portion provided on a first wiring layer included in the first wiring structure and a second connection portion provided on a second wiring layer included in the second wiring structure (see fig. 14, and illustration 2 above).
Yonemoto is not found disclosing expressly the limitation of, a first chip and a second chip layered on the first chip, wherein the first chip includes the first semiconductor layer, and wherein the second chip includes the second semiconductor layer.
However, Miyake discloses a first chip including the first semiconductor layer; and a second chip stacked on the first chip and including a second semiconductor layer (¶0018-0019).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement a stacked chip structure of Miyake having two or more chips stacked on top of another and placing respective semiconductor layers therein, to obtain, a first chip and a second chip layered on the first chip, wherein the first chip includes the first semiconductor layer, and wherein the second chip includes the second semiconductor layer.
However, Miyake discloses a first chip including the first semiconductor layer; and a second chip stacked on the first chip and including a second semiconductor layer, because, combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I).
Regarding claim 12, Yonemoto in view of Miyake discloses the photoelectric conversion device according to claim 11, further comprising a third chip (Miyaki fig. 3a, Yonemoto fig. 1),
wherein the third chip includes a third semiconductor layer (as an extension of combination done in claim 11, the limitation is understood met) including a second readout circuit (in this claim’s instance memory 62 function as second readout circuit, fig. 4) configured to read out the signal corresponding to the voltage held in the memory (in this claim’s instance, 41+42+43 function as memory, fig. 4, ¶0075-0084, ¶0135-0141), and a third wiring structure electrically connected with the second readout circuit (evident from figs 4, 14 of Yonemoto and figs. 3a, 22 of Miyaki).
Regarding claim 13, Yonemoto in view of Miyake discloses the photoelectric conversion device according to claim 12, wherein a signal that passes through a wiring line connected between the first chip and the second chip passes through a wiring line of the third chip (evident from figs 4, 14 of Yonemoto and figs. 3a, 22 of Miyaki).
Conclusion
The prior and/or pertinent art(s) made of record and not relied upon is considered pertinent to applicant's disclosure, are – MIYAUCHI et al. (US 20210099659 A1), Mori et al. (US 20190098232 A1), Keung et al. (US 20180227513 A1), and Fan (US 8773562 B1) – who disclose different image capturing devices of interest having stacked semiconductor layer architecture.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHBAZ NAZRUL whose telephone number is (571)270-1467. The examiner can normally be reached on M-Th: 9.30 am-3 pm, 6.30 pm-9 pm, F: 9.30 am-1.30 pm, 4 pm-8 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on (571)272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHBAZ NAZRUL/
Primary Examiner, Art Unit 2661
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