DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 7/7/2025 and 3/25/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities:
Claim 7 recite the limitation “thatthe” in line 6. It should be “that the”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hillier, III et al. (US 2006/0184846) and further in view of Zhuo et al. (US 2024/0152281).
As per claim 1, Hillier teaches a memory access method (Hillier: abstract), wherein the method comprises: receiving, by a [[cache]] controller, a memory access instruction sent by a processor core, wherein the memory access instruction is used to access a target memory space (Hillier: par. [0028]: “memory controller 105 receiving read and write requests”).
Hillier teaches a system with processor(s) including cache(s) (Hillier: fig. 1, items 102, 106, 108) and memory system having mirrored memory (Hillier: par. [0023]) where it is readily apparent that when memory access instruction is sent by the processor(s) 102, it is initially received by the caches and cache systems known to include cache controller.
Hillier fails to teach determining, by the cache controller based on mirroring indication information in a target cache line that is in a cache and that corresponds to the memory access instruction, whether the target memory space is a mirrored memory space.
Zhuo teaches a system with processors (Zhuo: par. [0052]) with cache and mirrored memory system (Zhuo: pars. [0058] – [0060). The mirroring also comprise mirroring indications to both page table entries (Zhuo: par. [0063]; figs. 5-7) and cache entries (Zhuo: par. [0064]; fig. 8). Zhuo expressly fails to teach determining, by the cache controller based on mirroring indication information in a target cache line that is in a cache and that corresponds to the memory access instruction, whether the target memory space is a mirrored memory space. However, as noted above, Zhuo teaches cache having cache lines with M bit indicating the cache entry is associated with mirrored memory space. Therefore, it would be readily apparent to one having ordinary skill in the art that when processor issues access request, the cache is checked for presence of the data and its associated entry field indicating whether the cache entry belongs to the mirrored memory space or non-mirrored space to provide better performance by accessing data indication from the cache instead of accessing the state information from the memory (Zhuo: par. [0059]).
As per claim 2, Hillier and Zhuo teach wherein the target cache line comprises a data area and a non-data area, the data area stores to-be-accessed data, the non-data area comprises a mirroring indication field, and the mirroring indication field is used to record the mirroring indication information (Zhuo: fig. 8 shows non-data area including flag bits, mirror indication bits and address tag and data area including data).
As per claim 3, Hillier and Zhuo expressly fail to teach wherein the method further comprises: determining that the target cache line does not exist in the cache; and in response to determining that the target cache line does not exist in the cache, determining, by the cache controller based on the mirroring indication information in a target non-data area that is in the target memory space and that corresponds to the memory access instruction, whether the target memory space is a mirrored memory space. However, Hillier and Zhuo teach system with processors, caches and mirrored memories. Zhuo also teaches the cache entries and page table entries comprising Mirror indication bits, where it would be readily apparent to one having ordinary skill in the art before the effective filing date of the claimed invention to determine that the target cache line does not exist in the cache and obtain the data from the mirrored memories with the indication that the target data belongs to the mirrored or non-mirrored memory space.
Claims 12-14 are directed to a processor comprising a cache and cache controller performing the method steps of claims 1-3 above. Hillier and Zhuo teach a processor and a cache. Thus, claims 12-14 are rejected under same rationales as applied to claims 1-3 respectively above.
Claim 20 is directed to a non-transitory computer readable medium and similar in scope with claim 1 above. Zhuo teaches a computer readable medium (par. [0151]). Thus, claim 20 is rejected under same rationales as applied to claim 1 above.
Claims 4-6, 9-11 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hillier, III et al. (US 2006/0184846) and Zhuo et al. (US 2024/0152281) as applied to claims 1, 3, 14 and 15 above, and further in view of Wu et al. (WO2022193768/CN11508223) (provided as IDS reference with English translation).
As per claim 4, Hillier and Zhuo fail to teach wherein the target memory space comprises a target data area and the target non-data area, the target data area stores to-be-accessed data, and the target non-data area stores the mirroring indication information. Wu teaches wherein the target memory space comprises a target data area and the target non-data area, the target data area stores to-be-accessed data, and the target non-data area stores the mirroring indication information (Wu: claim 5: ECC space includes mirror indication). Thus, it would have been obvious to one having ordinary skill in art before the effective filing date of the claimed invention to provide data area and non-data area including mirror indication as taught by Wu to provide an indication that allocated memory space belongs to mirrored space and perform the access accordingly.
As per claim 5, Hillier and Zhuo fail to teach wherein the method further comprises: determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a mirrored access mode; and in response to determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a mirrored access mode, performing, by the cache controller on the target memory space, an operation corresponding to the memory access instruction. Wu teaches wherein the method further comprises: determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a mirrored access mode; and in response to determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a mirrored access mode, performing, by the cache controller on the target memory space, an operation corresponding to the memory access instruction. Wu: (pars. [0063], [0064]) teaches that target memory space is mirrored space and the instruction indicates a mirrored access mode). Zhuo teaches performing an operation by the cache controller by loading data in the cache setting M bit flag to indicate that the data in the cache is associated with mirrored memory space. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide an instruction indicating mirrored access mode as taught by Wu so that system can identify whether the processor is performing operation related to mirrored memory space or normal memory space.
As per claim 6, Hillier and Zhuo fail to teach wherein the method further comprises: determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a non-mirrored access mode; and in response to determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a non-mirrored access mode, rejecting, by the cache controller, execution of the memory access instruction.
Wu teaches determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a non-mirrored access mode; and in response to determining that the target memory space is a mirrored memory space, and the memory access instruction indicates a non-mirrored access mode, rejecting, by the cache controller, execution of the memory access instruction (Wu: pars. [0063], [0064]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to identify non-mirrored access mode instruction and reject allowing access to mirrored space as taught by Wu to avoid the data corruption or data coherency because if non-mirrored instruction access the mirrored memory space.
As per claim 9, Hillier, Zhuo and Wu teach wherein the memory access instruction is a memory write instruction, the memory write instruction carries target data to be written, and the target memory space comprises a primary memory space and a secondary memory space; and the performing, by the cache controller on the target memory space, the operation corresponding to the memory access instruction comprises: sending, by the cache controller, a memory write notification to a memory controller, to indicate the memory controller to write the target data into both the primary memory space and the secondary memory space (Zhuo: pas. [0069] – [0071]; Wu: par. [0098]).
As per claim 10, Hillier, Zhuo and Wu teach wherein the method further comprises: receiving a memory allocation request of a target object, wherein the memory allocation request is used to request the target memory space (Zhuo: par. [0049]); and in response to a mirroring flag of the target object being set, allocating the target memory space to the target object, and setting the mirroring indication information in each non-data area in the target memory space (Wu: pars. [0108], [0109]).
As per claim 11, Hillier, Zhuo and Wu teach wherein the method further comprises: receiving a memory release request of the target object, wherein the memory release request is used to release the target memory space; and releasing the target memory space allocated to the target object, and canceling setting of the mirroring indication information in each non-data area in the target memory space (Zhuo: pars. [0049] – [0055]; Wu: par. [0108]).
Claims 15-17 are similar in scope with claims 4-6 above and thus rejected under same rationales as applied to claims 4-6 above respectively.
Allowable Subject Matter
Claims 7-8 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
As per claims 7 and 18, prior arts of record fail to teach or suggest wherein the rejecting, by the cache controller, execution of the memory access instruction comprises: obtaining, by the cache controller, mirroring configuration information of the target memory space, wherein the mirroring configuration information indicates whether access to the target memory space in the non-mirrored access mode is rejected; determining that the mirroring configuration information indicates that access to the target memory space in the non-mirrored access mode is rejected; and in response to determining that the mirroring configuration information indicates that access to the target memory space in the non-mirrored access mode is rejected, rejecting, by the cache controller, execution of the memory access instruction.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hum et al. (US 2014/0189417) teaches a method to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region.
Cox et al. (US 2014/0006729) teaches the memory controller configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device.
Jeter, Jr. et al. (US 2004/0186945) teaches a memory controller to write information mirrored to two memory banks and a processor issues a single write with mirror flag field asserted.
Bauman et al. (US 6,820,182) teaches a mirrored memory system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/ Primary Examiner, Art Unit 2138
Prosecution Insights