DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “display substrate”, “base substrate”, “circuit structure layer”, “the display substrate comprises: a base substrate and a circuit structure layer disposed on the base substrate” as recited in at least claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is AUTO-PROCESSED AND APPROVED IMMEDIATELY upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 6-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4-18 of U.S. Patent No. 12,367,823 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because as shown in the comparison table below it is clear that all the elements of the application claim are to be found in patent claim (as the application claim fully encompasses patent claim). The difference between the application claim and the patent claim lies in the fact that the patent claim includes many more elements and is thus much more specific. Thus, the invention of the patent claim is in effect a “species” of the “generic” invention of the application claim. It has been held that the generic invention is “anticipated” by the “species”. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993). Since application claim is anticipated by the patent claim, it is not patentably distinct from the patent claim.
Appl. No.: 19/221,559
Patent No.: US 12,367,823 B2
1. A display substrate, comprising a display region and a non-display region,
wherein the display substrate comprises:
a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer comprises:
a plurality of pixel circuits (P) arranged in an array and located in the display region and a plurality of drive circuits (GOA1 to GOAM) located in the non-display region;
at least one pixel circuit comprises a plurality of transistors, the plurality of drive circuits (GOA1 to GOAM) are configured to provide drive signals to the plurality of transistors;
the circuit structure layer further comprises:
a high-level power supply line (VHG) and a low-level power supply line (VGL) located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line (VHG) and the low-level power supply line (VGL) respectively;
wherein the plurality of transistors comprise:
a writing transistor (T4), a compensation transistor (T2), and a light emitting transistor (T5 or T6), and the plurality of drive circuits (GOA1 to GOAM) comprise:
a light emitting drive circuit (EM GOA), a scan drive circuit (GateN GOA) and a control drive circuit (GateP GOA);
the light emitting drive circuit (EM GOA) is configured to provide a drive signal to the light emitting transistor (T5 or T6), the control drive circuit (GateP GOA) is
configured to provide a drive signal to the writing transistor (T4)
and the scan drive circuit (GateN GOA) is configured to provide a drive signal to the compensation transistor (T2);
the light emitting drive circuit (EM GOA) and the scan drive circuit (GateN GOA) are configured to receive signals from a same high level power supply lines;
and the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA) are configured to receive signals from a same low level power supply lines.
6. The display substrate according to claim 1,
wherein when the high-level power supply line (VHG) connected with the light emitting drive circuit (EM GOA) and the high-level power supply line (VHG) connected with the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit (EM GOA) or the control drive circuit (GateP GOA) on the base substrate, or is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA).
7. The display substrate according to claim 1,
wherein when the low-level power supply line (VGL) connected with the light emitting drive circuit (EM GOA) and the low-level power supply line (VGL) connected with the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit (EM GOA) or the control drive circuit (GateP GOA) on the base substrate, or is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA).
8. The display substrate according to claim 1,
wherein the light emitting drive circuit (EM GOA) is located on a side of the control drive circuit (GateP GOA) away from the display region;
the circuit structure layer further comprises: a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, and a plurality of control clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines respectively, and the control drive circuit (GateP GOA) is electrically connected with the control initial signal line and the plurality of control clock signal lines respectively;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to or away from the display region;
and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region.
9. The display substrate according to claim 8,
wherein the light emitting drive circuit (EM GOA) comprises a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, and the control drive circuit (GateP GOA) comprises a plurality of control transistors and a plurality of control capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of control transistors, first electrode plates of the plurality of light emitting capacitors, and first electrode plates of the plurality of control capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors and second electrode plates of the plurality of control capacitors;
the third conductive layer comprises: source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s and source-drain electrodes of the plurality of control transistors;
the fourth conductive layer comprises a light emitting initial signal line, at least one light emitting clock signal line, a control initial signal line, and at least one control clock signal line.
10. The display substrate according to claim 1,
wherein the plurality of transistors further comprise:
a first reset transistor,
transistor types of the first reset transistor and the compensation transistor (T2) are different from transistor types of the writing transistor (T4) and the light emitting transistor (T5 or T6),
the scan drive circuit (GateN GOA) is further configured to provide a drive signal to the first reset transistor;
high-level power supply line (VHG)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line and/or low-level power supply line (VGL)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line.
11. The display substrate according to claim 10,
wherein when the high-level power supply line (VHG)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the high-level power supply line (VHG) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when high-level power supply line (VHG)s connected with the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the high-level power supply line (VHG) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
12. The display substrate according to claim 10,
wherein when the low-level power supply line (VGL)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the low-level power supply line (VGL) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when low-level power supply line (VGL)s connected with the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the low-level power supply line (VGL) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
13. The display substrate according to claim 10,
wherein the circuit structure layer further comprises a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a scan initial signal line, and a plurality of scan clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines respectively, the control drive circuit (GateP GOA) is electrically connected with the control initial signal line and the plurality of control clock signal lines respectively, and the scan drive circuit (GateN GOA) is electrically connected with the scan initial signal line and the plurality of scan clock signal lines respectively;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to the display region or away from the display region;
the control initial signal line and the plurality of control clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines close to the display region, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region;
and the scan initial signal line is located on a side of the plurality of scan clock signal lines close to the display region or away from the display region.
14. The display substrate according to claim 13,
wherein the light emitting drive circuit (EM GOA) comprises a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, the scan drive circuit (GateN GOA) comprises a plurality of scan transistors and a plurality of scan capacitors, and the control drive circuit (GateP GOA) comprises a plurality of control transistors and a plurality of control capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of scan transistors, gate electrodes of the plurality of control transistors, first electrode plates of the plurality of light emitting capacitors, first electrode plates of the plurality of scan capacitors, and first electrode plates of the plurality of control capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors, second electrode plates of the plurality of scan capacitors, and second electrode plates of the plurality of control capacitors;
the third conductive layer comprises: source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s, source-drain electrodes of the plurality of scan transistors, and source-drain electrodes of the plurality of control transistors;
and the fourth conductive layer comprises: a light emitting initial signal line, at least one light emitting clock signal line, a scan initial signal line, at least one scan clock signal line, a control initial signal line, and at least one control clock signal line.
15. The display substrate according to claim 1,
wherein the plurality of transistors further comprise:
a first reset transistor, and a second reset transistor;
the plurality of drive circuits (GOA1 to GOAM) further comprise a
first reset drive circuit, and a second reset drive circuit;
the first reset drive circuit is configured to provide a drive signal to the first reset transistor, and the second reset drive circuit is configured to provide a drive signal to the second reset transistor;
and high-level power supply line (VHG)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line and/or low-level power supply line (VGL)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line.
16. The display substrate according to claim 15,
wherein when the high-level power supply line (VHG)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the high-level power supply line (VHG) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when high-level power supply line (VHG)s connected with at least three adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the high-level power supply line (VHG) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
17. The display substrate according to claim 15,
wherein when the low-level power supply line (VGL)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the low-level power supply line (VGL) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when low-level power supply line (VGL)s connected with at least three adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the low-level power supply line (VGL) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
18. The display substrate according to claim 15,
wherein the light emitting drive circuit (EM GOA) is located on a side of the control drive circuit (GateP GOA) away from the display region, the first reset drive circuit is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA), and the second reset drive circuit is located on a side of the control drive circuit (GateP GOA) close to the display region;
the circuit structure layer further comprises a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a first reset initial signal line, a plurality of first reset clock signal lines, a second reset initial signal line, and a plurality of second reset clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is respectively electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines, the control drive circuit (GateP GOA) is respectively electrically connected with the control initial signal line and the plurality of control clock signal lines, the first reset drive circuit is respectively electrically connected with the first reset initial signal line and the plurality of first reset clock signal lines, and the second reset drive circuit is respectively electrically connected with the second reset initial signal line and the plurality of second reset clock signal lines;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to the display region or away from the display region;
the first reset initial signal line and the plurality of first reset clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines close to the display region, and the first reset initial signal line is located on a side of the plurality of first reset clock signal lines close to the display region or away from the display region;
the control initial signal line and the control clock signal lines are located on a side of the second reset initial signal line and the plurality of second reset clock signal lines away from the display region, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region;
and the second reset initial signal line is located on a side of the plurality of second reset clock signal lines close to the display region or away from the display region.
19. The display substrate according to claim 18,
wherein the light emitting drive circuit (EM GOA) comprises: a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, the scan drive circuit (GateN GOA) comprises a plurality of scan transistors and a plurality of scan capacitors, the first reset drive circuit comprises a plurality of first reset transistors and a plurality of first reset capacitors, and the second reset drive circuit comprises a plurality of second reset transistors and a plurality of second reset capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of control transistors, gate electrodes of the plurality of first reset transistors, gate electrodes of the plurality of second reset transistors, first electrode plates of the plurality of light emitting capacitors, first electrode plates of the plurality of control capacitors, first electrode plates of the plurality of first reset capacitors, and first electrode plates of the plurality of second reset capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors, second electrode plates of the plurality of control capacitors, second electrode plates of the plurality of first reset capacitors, and second electrode plates of the plurality of second reset capacitors;
the third conductive layer comprises source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s, source-drain electrodes of the plurality of control transistors, source-drain electrodes of the plurality of first reset transistors, and source-drain electrodes of the plurality of second reset transistors;
and the fourth conductive layer comprises a light emitting initial signal line, at least one light emitting clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.
20. A display apparatus, comprising a display substrate according to claim 1.
1. A display substrate, comprising
a display region and a non-display region,
wherein; the display substrate comprises:
a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer comprises:
a plurality of pixel circuits (P) arranged in an array and located in the display region and a plurality of drive circuits (GOA1 to GOAM) located in the non-display region;
at least one pixel circuit comprises a plurality of transistors, the plurality of drive circuits (GOA1 to GOAM) are configured to provide drive signals to the plurality of transistors;
the circuit structure layer further comprises:
a high-level power supply line (VHG) and a low-level power supply line (VGL) located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line (VHG) and the low-level power supply line (VGL) respectively,
and the high-level power supply line (VHG) and the low-level power supply line (VGL) extend along a first direction;
high-level power supply line (VHG)s connected with at least two drive circuits (GOA1 to GOAM) are a same power supply line and/or low-level power supply line (VGL)s connected with at least two drive circuits (GOA1 to GOAM) are a same power supply line;
the circuit structure layer comprises:
a semiconductor layer, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer, a third conductive layer, a fourth insulation layer, and a fourth conductive layer that are sequentially stacked on the base substrate;
the high-level power supply line (VHG) and the low-level power supply line (VGL) are located in the third conductive layer and/or the fourth conductive layer;
the plurality of transistors comprise:
a writing transistor (T4), a compensation transistor (T2), and a light emitting transistor (T5 or T6), and the plurality of drive circuits (GOA1 to GOAM) comprise:
a light emitting drive circuit (EM GOA) and a control drive circuit (GateP GOA);
the light emitting drive circuit (EM GOA) is configured to provide a drive signal to the light emitting transistor (T5 or T6), and the control drive circuit (GateP GOA) is configured to provide a drive signal to the writing transistor (T4)
and/or the compensation transistor (T2);
and a high-level power supply line (VHG) connected with the light emitting drive circuit (EM GOA) and a high-level power supply line (VHG) connected with the control drive circuit (GateP GOA) are a same power supply line
and/or a low-level power supply line (VGL) connected with the light emitting drive circuit (EM GOA) and a low-level power supply line (VGL) connected with the control drive circuit (GateP GOA) are a same power supply line.
4. The display substrate according to claim 1,
wherein when the high-level power supply line (VHG) connected with the light emitting drive circuit (EM GOA) and the high-level power supply line (VHG) connected with the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit (EM GOA) or the control drive circuit (GateP GOA) on the base substrate, or is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA).
5. The display substrate according to claim 1,
wherein when the low-level power supply line (VGL) connected with the light emitting drive circuit (EM GOA) and the low-level power supply line (VGL) connected with the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit (EM GOA) or the control drive circuit (GateP GOA) on the base substrate, or is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA).
6. The display substrate according to claim 1,
wherein the light emitting drive circuit (EM GOA) is located on a side of the control drive circuit (GateP GOA) away from the display region;
the circuit structure layer further comprises: a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, and a plurality of control clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines respectively, and the control drive circuit (GateP GOA) is electrically connected with the control initial signal line and the plurality of control clock signal lines respectively;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to or away from the display region;
and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region.
7. The display substrate according to claim 6,
wherein the light emitting drive circuit (EM GOA) comprises a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, and the control drive circuit (GateP GOA) comprises a plurality of control transistors and a plurality of control capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of control transistors, first electrode plates of the plurality of light emitting capacitors, and first electrode plates of the plurality of control capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors and second electrode plates of the plurality of control capacitors;
the third conductive layer comprises: source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s and source-drain electrodes of the plurality of control transistors;
the fourth conductive layer comprises a light emitting initial signal line, at least one light emitting clock signal line, a control initial signal line, and at least one control clock signal line.
8. The display substrate according to claim 1,
wherein the plurality of transistors comprise:
a writing transistor (T4),
a first reset transistor,
a compensation transistor (T2), and a light emitting transistor (T5 or T6),
transistor types of the first reset transistor and the compensation transistor (T2) are different from transistor types of the writing transistor (T4) and the light emitting transistor (T5 or T6), the plurality of drive circuits (GOA1 to GOAM) comprise: a light emitting drive circuit (EM GOA), a scan drive circuit (GateN GOA), and a control drive circuit (GateP GOA);
the light emitting drive circuit (EM GOA) is configured to provide a drive signal to the light emitting transistor (T5 or T6), the control drive circuit (GateP GOA) is configured to provide a drive signal to the writing transistor (T4), and
the scan drive circuit (GateN GOA) is configured to
provide a drive signal to the first reset transistor and/or the compensation transistor (T2);
high-level power supply line (VHG)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line and/or low-level power supply line (VGL)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line.
9. The display substrate according to claim 8,
wherein when the high-level power supply line (VHG)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the high-level power supply line (VHG) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when high-level power supply line (VHG)s connected with the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the high-level power supply line (VHG) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
10. The display substrate according to claim 8,
wherein when the low-level power supply line (VGL)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the low-level power supply line (VGL) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when low-level power supply line (VGL)s connected with the light emitting drive circuit (EM GOA), the scan drive circuit (GateN GOA), and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the low-level power supply line (VGL) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
11. The display substrate according to claim 8,
wherein the light emitting drive circuit (EM GOA) is located on a side of the scan drive circuit (GateN GOA) away from the display region, and the control drive circuit (GateP GOA) is located on a side of the scan drive circuit (GateN GOA) close to the display region;
the circuit structure layer further
comprises a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a scan initial signal line, and a plurality of scan clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines respectively, the control drive circuit (GateP GOA) is electrically connected with the control initial signal line and the plurality of control clock signal lines respectively, and the scan drive circuit (GateN GOA) is electrically connected with the scan initial signal line and the plurality of scan clock signal lines respectively;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to the display region or away from the display region;
the control initial signal line and the plurality of control clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines close to the display region, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region;
and the scan initial signal line is located on a side of the plurality of scan clock signal lines close to the display region or away from the display region.
12. The display substrate according to claim 11,
wherein the light emitting drive circuit (EM GOA) comprises a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, the scan drive circuit (GateN GOA) comprises a plurality of scan transistors and a plurality of scan capacitors, and the control drive circuit (GateP GOA) comprises a plurality of control transistors and a plurality of control capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of scan transistors, gate electrodes of the plurality of control transistors, first electrode plates of the plurality of light emitting capacitors, first electrode plates of the plurality of scan capacitors, and first electrode plates of the plurality of control capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors, second electrode plates of the plurality of scan capacitors, and second electrode plates of the plurality of control capacitors;
the third conductive layer comprises: source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s, source-drain electrodes of the plurality of scan transistors, and source-drain electrodes of the plurality of control transistors;
and the fourth conductive layer comprises: a light emitting initial signal line, at least one light emitting clock signal line, a scan initial signal line, at least one scan clock signal line, a control initial signal line, and at least one control clock signal line.
13. The display substrate according to claim 1,
wherein the plurality of transistors comprise: a writing transistor (T4), a compensation transistor (T2),
a first reset transistor, a second reset
transistor,
and a light emitting transistor (T5 or T6);
the plurality of drive circuits (GOA1 to GOAM) comprise
a light emitting drive circuit (EM GOA),
a first reset drive circuit, a second reset drive circuit, and
a control drive circuit (GateP GOA);
the light emitting drive circuit (EM GOA) is configured to provide a drive signal to the light emitting transistor (T5 or T6), the control drive circuit (GateP GOA) is configured to provide a drive signal to the writing transistor (T4) and/or the compensation transistor (T2),
the first reset drive circuit is configured to provide a drive signal to the first reset transistor, and the second reset drive circuit is configured to provide a drive signal to the second reset transistor;
and high-level power supply line (VHG)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line and/or low-level power supply line (VGL)s connected with at least two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line.
14. The display substrate according to claim 13,
wherein when the high-level power supply line (VHG)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the high-level power supply line (VHG) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when high-level power supply line (VHG)s connected with at least three adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the high-level power supply line (VHG) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the high-level power supply line (VHG) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
15. The display substrate according to claim 13,
wherein when the low-level power supply line (VGL)s connected with two adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are the same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) connected with the low-level power supply line (VGL) on the base substrate, or is located between the connected two adjacent drive circuits (GOA1 to GOAM);
or, when low-level power supply line (VGL)s connected with at least three adjacent drive circuits (GOA1 to GOAM) in the light emitting drive circuit (EM GOA), the first reset drive circuit, the second reset drive circuit, and the control drive circuit (GateP GOA) are a same power supply line, an orthographic projection of the low-level power supply line (VGL) on the base substrate is partially overlapped with an orthographic projection of one of the drive circuits (GOA1 to GOAM) with which the low-level power supply line (VGL) is connected on the base substrate, or is located between two adjacent drive circuits (GOA1 to GOAM).
16. The display substrate according to claim 13,
wherein the light emitting drive circuit (EM GOA) is located on a side of the control drive circuit (GateP GOA) away from the display region, the first reset drive circuit is located between the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA), and the second reset drive circuit is located on a side of the control drive circuit (GateP GOA) close to the display region;
the circuit structure layer further comprises a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a first reset initial signal line, a plurality of first reset clock signal lines, a second reset initial signal line, and a plurality of second reset clock signal lines which are located in the non-display region and extending along the first direction;
the light emitting drive circuit (EM GOA) is respectively electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines, the control drive circuit (GateP GOA) is respectively electrically connected with the control initial signal line and the plurality of control clock signal lines, the first reset drive circuit is respectively electrically connected with the first reset initial signal line and the plurality of first reset clock signal lines, and the second reset drive circuit is respectively electrically connected with the second reset initial signal line and the plurality of second reset clock signal lines;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to the display region or away from the display region;
the first reset initial signal line and the plurality of first reset clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines close to the display region, and the first reset initial signal line is located on a side of the plurality of first reset clock signal lines close to the display region or away from the display region;
the control initial signal line and the control clock signal lines are located on a side of the second reset initial signal line and the plurality of second reset clock signal lines away from the display region, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region;
and the second reset initial signal line is located on a side of the plurality of second reset clock signal lines close to the display region or away from the display region.
17. The display substrate according to claim 16,
wherein the light emitting drive circuit (EM GOA) comprises: a plurality of light emitting transistor (T5 or T6)s and a plurality of light emitting capacitors, the scan drive circuit (GateN GOA) comprises a plurality of scan transistors and a plurality of scan capacitors, the first reset drive circuit comprises a plurality of first reset transistors and a plurality of first reset capacitors, and the second reset drive circuit comprises a plurality of second reset transistors and a plurality of second reset capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistor (T5 or T6)s, gate electrodes of the plurality of control transistors, gate electrodes of the plurality of first reset transistors, gate electrodes of the plurality of second reset transistors, first electrode plates of the plurality of light emitting capacitors, first electrode plates of the plurality of control capacitors, first electrode plates of the plurality of first reset capacitors, and first electrode plates of the plurality of second reset capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors, second electrode plates of the plurality of control capacitors, second electrode plates of the plurality of first reset capacitors, and second electrode plates of the plurality of second reset capacitors;
the third conductive layer comprises source-drain electrodes of the plurality of light emitting transistor (T5 or T6)s, source-drain electrodes of the plurality of control transistors, source-drain electrodes of the plurality of first reset transistors, and source-drain electrodes of the plurality of second reset transistors;
and the fourth conductive layer comprises a light emitting initial signal line, at least one light emitting clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.
18. A display apparatus, comprising a display substrate according to claim 1.
Comparison table 1
Allowable Subject Matter
Claims 1-20 are allowed if the double patenting rejection above is overcome (e.g., an e-TD is filed).
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1:
The prior art, [Wang; Seong Min et al., US 20210264857 A1], discloses:
“The power supply 180 may provide the high power supply voltage ELVDD, the low power supply voltage ELVSS, the first initialization voltage VINT, the second initialization voltage AINT, and the bias voltage Vb to the display panel 110, and may further provide the first voltage VGH and the second voltage VGL to the emission driver 300 and the scan driver 200, in response to a power control signal PCTL”, as recited in ¶ 0061.
However, the prior art does not teach or suggest either singularly or in combination the at least claimed “the light emitting drive circuit (EM GOA) is configured to provide a drive signal to the light emitting transistor (T5 or T6), the control drive circuit (GateP GOA) is configured to provide a drive signal to the writing transistor (T4) and the scan drive circuit (GateN GOA) is configured to provide a drive signal to the compensation transistor (T2); the light emitting drive circuit (EM GOA) and the scan drive circuit (GateN GOA) are configured to receive signals from a same high level power supply lines;
and the light emitting drive circuit (EM GOA) and the control drive circuit (GateP GOA) are configured to receive signals from a same low level power supply lines”, in combination with the other recited claim features.
Regarding claim 2-20:
Claim(s) 2-20 depend(s) on claim 1 and is/are found allowable for at least the same reason as discussed above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Wang; Seong Min et al., US 20210264857 A1] discloses:
“The power supply 180 may provide the high power supply voltage ELVDD, the low power supply voltage ELVSS, the first initialization voltage VINT, the second initialization voltage AINT, and the bias voltage Vb to the display panel 110, and may further provide the first voltage VGH and the second voltage VGL to the emission driver 300 and the scan driver 200, in response to a power control signal PCTL”, as recited in ¶ 0061.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Koosha Sharifi-Tafreshi whose telephone number is (571)270-5897. The examiner can normally be reached Mon - Fri 8AM to 5PM EST.
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628