DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/08/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 17-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal et al. (US2019/0079868) in view of Gilbert et al. (US7,581,068).
With respect to claim 1, Jalal et al. teaches accessing a system-on-a-chip (SoC) (see Fig. 1 and paragraph 15; system 100 may be implemented in a system-on-a-Chip (SoC)), wherein the SoC includes one or more cache coherency blocks (CCBs) (see Fig. 1 and paragraph 15; blocks 102 and 104 are referred to herein as request nodes (RN's) that may generate requests for data transactions) and one or more coherency ordering agents (COAs) (see Fig. 1 and paragraph 15; home nodes 108), wherein each COA within the one or more COAs includes a directory snoop filter (DSF) (see Fig. 1 and paragraph 19; home node 108 also includes a snoop filter 400 that monitors data transactions and maintains the status of data stored in the system cache 116), and wherein each CCB within the one or more CCBs is communicatively coupled to each COA within the one or more COAs by a network-on-a-chip (NOC) interface (see Fig. 1 and paragraph 15; on-chip interconnect 106);
requesting, by a first CCB within the one or more CCBs, a cache line associated with a memory address (see paragraph 43; request, sent from an RN-F to the HN-F, to access data at an address in system memory), wherein the first CCB is not a sharer of the cache line (see paragraph 43; If the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508. If the address is not found in the cache (a cache ‘miss’), flow continues to decision block 510 to determine, from the snoop filter, if any other caches contain the requested data (i.e., requesting node does not contain the requested data));
reading, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line (see paragraphs 44 and 50-52; If the address is found in the snoop filter (a snoop filter ‘hit’), as indicated by the positive branch from decision block 510, the data is stored in a RN-F cache and a snoop is sent at block 520 to the corresponding RN-F. The snoop is sent to all nodes that share the data); and wherein the first COA includes a coherent last level cache (LLC) that contains a valid copy of the cache line (see paragraphs 19 and 44; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node); and
forwarding the cache line, by the coherent LLC, to the first CCB (see paragraph 45; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node. The snoop filter (SF) is updated at block 526 to indicate that the requesting RN-F will have a copy of the data).
Jalal et al. does not explicitly teach reading, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line, wherein the reading indicates that there is no CCB owner of the cache line; and assigning, by the first COA, to the first CCB, an ownership of the cache line, wherein the assigning is recorded in the DSF.
However, Gilbert et al. teaches coherency engine 23 receives a request from one of processors or I/O devices for a memory transaction. At block 320, coherency engine 23 looks up snoop filter 24 to determine if the requested line has an entry in the snoop filter…if requested line does not have an entry in snoop filter 24, coherency engine 23 determines if the request may cause the line to become exclusively owned by a processor at block 350 (i.e., no processor or I/O device owns the cache line) (see column 5, lines 58-67 and column 6, lines 1-5); and if the line will become exclusively owned by a processor, at block 360, coherency engine 23 allocates an entry to the requested line (i.e., requesting processor is assign ownership of cache line and snoop filter is updated) (see column 6, lines 5-9).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. to include the above mentioned to improve overall system performance (see Gilbert, column 3, lines 51-54).
With respect to claim 2, Jalal et al. teaches wherein the cache line was previously evicted from a previous CCB owner (see paragraphs 54-55; when a subsequent WriteBack request is received from RNF0 after the data has been evicted from the system cache. The writeBack request again indicates that the data is in an SD state from RNF0. The snoop filter state is SC, which indicates to the snoop filter control logic that the system cache previously held a ‘dirty’ copy of the data and has evicted it to memory… presence vector in the SF is updated, to indicate that RNF0 no longer shares the data, and the data is stored in the system cache and marked ‘dirty’. RNF0 updates the state of the data in its local cache to ‘Invalid’ (i.e., cache line previously evicted)).
With respect to claim 17, Jalal et al. teaches wherein the requesting includes determining, by the first CCB, to access the first COA, wherein the determining is based on the memory address (see paragraphs 43 and 45; request, sent from an RN-F to the HN-F, to access data at an address in system memory, the address is looked-up in the system cache of the HN-F and in the snoop filter (SF) at block 504. If the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508… If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache of the HN-F node. The snoop filter (SF) is updated at block 526 to indicate that the requesting RN-F will have a copy of the data and the data is forwarded to the RN-F node).
With respect to claim 18, Jalal et al. teaches wherein the DSF includes sharing and owner information for each shared cache line within a hierarchical coherent cache coupled to each CCB in the one or more CCBs (see paragraph 27; snoop filter cache 302 contains a number of records 308 associated with cached data in the system. Each record 308 comprises tag field 310, which identifies the associated data, a cache coherence status field 312 that indicates the MOESI state of the data, an RNF-ID field 314 that identifies the owner of any SharedDirty (SD) or Owned data, and a presence vector 316. The presence vector 316 contains bits that indicate which nodes of the system have the data in their local cache).
With respect to claim 19, Jalal et al. teaches wherein the first COA manages coherency between the one or more CCBs and other coherent caches within the SoC (see paragraph 19; a home node 108 also includes a snoop filter 400 that monitors data transactions and maintains the status of data stored in the system cache 116 and operates to maintain coherency of data in the various caches of the system).
With respect to claim 20, Jalal et al. teaches wherein the first CCB manages coherency between one or more processor cores on a multicore processor (see paragraphs 15 and 18; requesting nodes 102 each comprising cluster of processing cores (CPU's) that share an L2 cache, with each processing core having its own L1 cache… to maintain coherence, each RN includes a cache controller 114 that accepts load and store instructions from the processor cores. The cache controller 114 also issues and receives coherence requests and responses via the interconnect circuit 106 from other nodes).
With respect to claim 21, Jalal et al. teaches accessing a system-on-a-chip (SoC) (see Fig. 1 and paragraph 15; system 100 may be implemented in a system-on-a-Chip (SoC)), wherein the SoC includes one or more cache coherency blocks (CCBs) (see Fig. 1 and paragraph 15; blocks 102 and 104 are referred to herein as request nodes (RN's) that may generate requests for data transactions) and one or more coherency ordering agents (COAs) (see Fig. 1 and paragraph 15; home nodes 108), wherein each COA within the one or more COAs includes a directory snoop filter (DSF) (see Fig. 1 and paragraph 19; home node 108 also includes a snoop filter 400 that monitors data transactions and maintains the status of data stored in the system cache 116), and wherein each CCB within the one or more CCBs is communicatively coupled to each COA within the one or more COAs by a network-on-a-chip (NOC) interface (see Fig. 1 and paragraph 15; on-chip interconnect 106);
requesting, by a first CCB within the one or more CCBs, a cache line associated with a memory address (see paragraph 43; request, sent from an RN-F to the HN-F, to access data at an address in system memory), wherein the first CCB is not a sharer of the cache line (see paragraph 43; If the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508. If the address is not found in the cache (a cache ‘miss’), flow continues to decision block 510 to determine, from the snoop filter, if any other caches contain the requested data (i.e., requesting node does not contain the requested data));
reading, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line (see paragraphs 44 and 50-52; If the address is found in the snoop filter (a snoop filter ‘hit’), as indicated by the positive branch from decision block 510, the data is stored in a RN-F cache and a snoop is sent at block 520 to the corresponding RN-F. The snoop is sent to all nodes that share the data); and wherein the first COA includes a coherent last level cache (LLC) that contains a valid copy of the cache line (see paragraphs 19 and 44; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node); and
forwarding the cache line, by the coherent LLC, to the first CCB (see paragraph 45; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node. The snoop filter (SF) is updated at block 526 to indicate that the requesting RN-F will have a copy of the data).
Jalal et al. does not explicitly teach reading, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line, wherein the reading indicates that there is no CCB owner of the cache line; and assigning, by the first COA, to the first CCB, an ownership of the cache line, wherein the assigning is recorded in the DSF.
However, Gilbert et al. teaches coherency engine 23 receives a request from one of processors or I/O devices for a memory transaction. At block 320, coherency engine 23 looks up snoop filter 24 to determine if the requested line has an entry in the snoop filter…if requested line does not have an entry in snoop filter 24, coherency engine 23 determines if the request may cause the line to become exclusively owned by a processor at block 350 (i.e., no processor or I/O device owns the cache line) (see column 5, lines 58-67 and column 6, lines 1-5); and if the line will become exclusively owned by a processor, at block 360, coherency engine 23 allocates an entry to the requested line (i.e., requesting processor is assign ownership of cache line and snoop filter is updated) (see column 6, lines 5-9).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jalal et al. to include the above mentioned to improve overall system performance (see Gilbert, column 3, lines 51-54).
With respect to claim 22, Jalal et al. teaches a memory which stores instructions (see paragraph 61; programming instructions that are broadly described in flow chart form that can be stored on any suitable electronic storage medium); and
one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored (see paragraph 61; programmed processors executing programming instructions that are broadly described in flow chart form that can be stored on any suitable electronic storage medium), are configured to:
access a system-on-a-chip (SoC) (see Fig. 1 and paragraph 15; system 100 may be implemented in a system-on-a-Chip (SoC)), wherein the SoC includes one or more cache coherency blocks (CCBs) (see Fig. 1 and paragraph 15; blocks 102 and 104 are referred to herein as request nodes (RN's) that may generate requests for data transactions) and one or more coherency ordering agents (COAs) (see Fig. 1 and paragraph 15; home nodes 108), wherein each COA within the one or more COAs includes a directory snoop filter (DSF) (see Fig. 1 and paragraph 19; home node 108 also includes a snoop filter 400 that monitors data transactions and maintains the status of data stored in the system cache 116), and wherein each CCB within the one or more CCBs is communicatively coupled to each COA within the one or more COAs by a network-on-a-chip (NOC) interface (see Fig. 1 and paragraph 15; on-chip interconnect 106);
request, by a first CCB within the one or more CCBs, a cache line associated with a memory address (see paragraph 43; request, sent from an RN-F to the HN-F, to access data at an address in system memory), wherein the first CCB is not a sharer of the cache line (see paragraph 43; If the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508. If the address is not found in the cache (a cache ‘miss’), flow continues to decision block 510 to determine, from the snoop filter, if any other caches contain the requested data (i.e., requesting node does not contain the requested data));
read, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line (see paragraphs 44 and 50-52; If the address is found in the snoop filter (a snoop filter ‘hit’), as indicated by the positive branch from decision block 510, the data is stored in a RN-F cache and a snoop is sent at block 520 to the corresponding RN-F. The snoop is sent to all nodes that share the data); and wherein the first COA includes a coherent last level cache (LLC) that contains a valid copy of the cache line (see paragraphs 19 and 44; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node); and
forward the cache line, by the coherent LLC, to the first CCB (see paragraph 45; If the address is found in the cache (a cache ‘hit’), as indicated by the positive branch from decision block 508, the data is already stored in the system cache (i.e., LLC) of the HN-F node. The snoop filter (SF) is updated at block 526 to indicate that the requesting RN-F will have a copy of the data).
Jalal et al. does not explicitly teach read, within a first COA, a directory snoop filter (DSF), wherein the reading reveals one or more CCB sharers of the cache line, wherein the reading indicates that there is no CCB owner of the cache line; and assign, by the first COA, to the first CCB, an ownership of the cache line, wherein the assigning is recorded in the DSF.
However, Gilbert et al. teaches coherency engine 23 receives a request from one of processors or I/O devices for a memory transaction. At block 320, coherency engine 23 looks up snoop filter 24 to determine if the requested line has an entry in the snoop filter…if requested line does not have an entry in snoop filter 24, coherency engine 23 determines if the request may cause the line to become exclusively owned by a processor at block 350 (i.e., no processor or I/O device owns the cache line) (see column 5, lines 58-67 and column 6, lines 1-5); and if the line will become exclusively owned by a processor, at block 360, coherency engine 23 allocates an entry to the requested line (i.e., requesting processor is assign ownership of cache line and snoop filter is updated) (see column 6, lines 5-9).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jalal et al. to include the above mentioned to improve overall system performance (see Gilbert, column 3, lines 51-54).
Claim(s) 3-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal et al. (US2019/0079868) and Gilbert et al. (US7,581,068) as applied to claim 1 above, and further in view of Li et al. (US2024/0244013).
With respect to claim 3, Jalal et al. and Gilbert et al. do not teach wherein the NOC interface includes an M x N mesh topology.
However, Li et al. teaches wherein a topology of the NoC may be a 2D/3D mesh network (see paragraphs 37-39 and 112).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. and Gilbert et al. to include the above mentioned so that the nodes can communicate reliably (see Li, paragraph 38).
With respect to claim 4, Jalal et al. and Gilbert et al. do not teach wherein the M x N mesh topology includes a coherent tile at each point of the M x N mesh topology.
However, Li et al. teaches wherein a topology of the NoC may be a 2D/3D mesh network… NoC connects a plurality of nodes on a chip together, so that the nodes can communicate reliably (see paragraphs 37-39 and 112).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. and Gilbert et al. to include the above mentioned so that the nodes can communicate reliably (see Li, paragraph 38).
With respect to claim 5, Jalal et al. teaches wherein the first COA is located on a different coherent tile than the first CCB Fig. 1 and paragraph 15; blocks 102 and 104 are referred to herein as request nodes (RN's) and home nodes (HN) are located in different nodes/tiles).
With respect to claim 6, Jalal et al. does explicitly not teach wherein the requesting comprises a request to own the cache line associated with the memory address.
However, Gilbert et al. teaches coherency engine 23 receives a request from one of processors or I/O devices for a memory transaction. At block 320, coherency engine 23 looks up snoop filter 24 to determine if the requested line has an entry in the snoop filter…if requested line does not have an entry in snoop filter 24, coherency engine 23 determines if the request may cause the line to become exclusively owned by a processor at block 350; and if the line will become exclusively owned by a processor, at block 360, coherency engine 23 allocates an entry to the requested line (i.e., request may include assigning ownership of cache line) (see column 6, lines 5-9).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. to include the above mentioned to improve overall system performance (see Gilbert, column 3, lines 51-54).
With respect to claim 7, Jalal et al. does not explicitly teach wherein the forwarding includes sending, by the first COA, an invalidating snoop to the one or more CCB sharers of the cache line.
However, Gilbert et al. teaches wherein the forwarding includes sending, by the first COA, an invalidating snoop to the one or more CCB sharers of the cache line (see Table 1 and column 5, lines 27-41; write-invalidate request sends an invalidating snoop to cache line owner or all agents).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. to include the above mentioned to improve overall system performance (see Gilbert, column 3, lines 51-54).
With respect to claim 8, Jalal et al. teaches wherein the one or more CCB sharers of the cache line are indicated by a presence vector within the DSF (see paragraphs 27 and 51-52; presence vector 316 contains bits that indicate which nodes of the system have the data in their local cache… HNF snoop filter will mark both RNF0 and RNF1 as a sharer of the cache data, as indicated by the SF presence vector).
With respect to claim 9, Jalal et al. teaches back invalidating, by each CCB sharer within the one or more CCB sharers, a local cache line within a coherent cache which contains a copy of the data associated with the memory address (see paragraphs 54-55; writeback request is received from RNF0 before the data has been evicted from the system cache. The snoop controller determines that the data is already in the system cache in a ‘dirty’ state, and so the data is dropped and no changes are made to the cache. The snoop filter presence vector is updated to indicate that RNF0 no longer shares the data. RNF0 updates the state of the data in its local cache to ‘Invalid (i.e., request nodes containing copy of the cache line are invalidated)).
With respect to claim 10, Jalal et al. teaches wherein the sending the invalidating snoop is based on a local snoop vector (see paragraph 54; writeback request again indicates that the data is in an SD state from RNF0. The snoop filter state is SC, which indicates to the snoop filter control logic that the system cache previously held a ‘dirty’ copy of the data and has evicted it to memory (i.e., invalidation is based on information stored in an entry of snoop filter)).
With respect to claim 11, Jalal et al. and Gilbert et al. do not teach wherein the local snoop vector enables communication between coherent tiles in the M x N mesh topology.
However, Li et al. teaches wherein a topology of the NoC may be a 2D/3D mesh network… NoC connects a plurality of nodes on a chip together, so that the nodes can communicate reliably (see paragraphs 37-39 and 112).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jalal et al. and Gilbert et al. to include the above mentioned so that the nodes can communicate reliably (see Li, paragraph 38).
With respect to claim 12, Jalal et al. teaches generating a snoop vector (see paragraph 27; snoop filter 300 includes a snoop filter cache 302 and snoop filter control logic 304 that generates snoop signals at output 306... A snoop signal may be a request for data associated with a particular address. Such a snoop signal is referred to simply as a ‘snoop’. The snoop filter cache 302 contains a number of entries/records (i.e., vectors) associated with cached data in the system)
With respect to claim 13, Jalal et al. teaches wherein the snoop vector includes the one or more CCB sharers of the cache line (see paragraphs 19-20, 27 and 38; where each entry (i.e., snoop vector) of the snoop filter contains a tag field identifying the associated data/memory address. The snoop filter tracks the status of all the data stored in the caches in the nodes. Each entry also identifies the owner of any shared-dirty, or owned data as well as a presence vector that indicates which nodes of the system have the data in their local caches).
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Sherman et al. (US 5,659,710) teaches snoop monitor logic monitors a coherent memory transaction on the system bus and broadcasts in response thereto a unidirectional snoop response signal with reference to the associated bus master's cache means, i.e., when the coherent memory transaction is initiated by another bus master. The snoop monitors are electrically interconnected such that each snoop monitor receives at separate single signal inputs the unidirectional snoop response signals generated in response to the coherent memory transaction on the system bus.
However, Sherman does not teach creating a directional snoop vector (DSV) as recited in claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Vash et al. (US2023/0169003) teaches a scalable cache coherency protocol.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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