DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8-14, 16, 17, 19 and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 7,434,122), and further in view of Raghu et al. (US 8,902,658).
Consider claim 1, Jo discloses a method comprising: obtaining a memory failed row address of a memory; obtaining an address mapping table comprising a mapping relationship between the memory failed row address and a first memory remapping row address, wherein the first memory remapping row address indicates a memory area in a reserved space of the memory; obtaining, when an access target of the memory is the memory failed row address, the first memory remapping row address based on the mapping relationship (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead.)
As for the new limitations: “performing an access test on the memory failed row address to determine whether the memory failed row address is a real failed row address; and releasing, when the memory failed row address is not the real failed row address, the memory failed row address and the first memory remapping row address from the address mapping table”, Jo does not disclose testing memory locations that have been identified as failed to determine if they are actually failed memory locations and removing them as failed if they pass a test, however, Raghu et al. (Col. 1 lines 47-61, Col. 6 lines 49-52, Col. 12 lines 43-57 and Col. 14 lines 53-61) discloses a FLASH memory that starts with a default set of erase conditions based on the memory being new and as the memory becomes worn the default set of erase conditions no longer work well leading to erase blocks being marked bad and placed on a list. Then when a second set of erase conditions would provide better results, the second set of erase conditions are utilized and erase blocks put on a bad block list during the default set of erase conditions are re-tested under the second set of erase conditions and if the erase block works, then they can be removed from the bad block list and put back to use.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Jo reference to include the erase block conditioning settings and retesting erase blocks as the erase block condition settings change as is done in Raghu et al. because doing so allows for adjustments to erase block conditions that can alleviate issues related to erase block wear so that erase blocks that might still have use left can still be effectively used, thus improving memory performance and lifetime (Raghu et al.: Col. 12 lines 30-34 and 43-64).
Consider claim 2, Jo discloses the method of claim 1, further comprising: obtaining a memory access address from outside of the memory; performing matching on the memory access address using the address mapping table; and translating, when the memory access address matches the memory failed row address, access to the memory access address into access to the first memory remapping row address (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead.).
Consider claim 3, Jo in view of Raghu et al. discloses the method of claim 1, wherein the memory comprises a plurality of memory chips, and wherein obtaining the first memory remapping row address comprises translating, when a failed row occurs in one of the memory chips, row addresses in the memory chips into second memory remapping row addresses comprising the failed row (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead. Jo only discloses one memory cell array. Raghu et al.: Col. 5 line 20 discloses one or more integrated circuit chips.).
Consider claim 5, Jo discloses the method of claim 1, further comprising: storing the address mapping table in a volatile memory in a matching and searching circuit; writing, before the memory stops working, the address mapping table into a non-volatile memory; and loading, after the non-volatile memory starts to work, the address mapping table to the matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table to register storage on boot up and moving back to non-volatile before power is removed. The circuitry that performs these functions are considered part of the claimed matching and searching circuit.).
Consider claim 6, Jo discloses the method of claim 5, wherein in a start process of a computing device loaded with the memory, the method further comprises: reading the address mapping table from the non-volatile memory; and updating the address mapping table through memory self-check of the computing device (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table form non-volatile memory and the bad block mapping table is updated based on the state of the memory.).
Consider claim 8, Jo discloses the method of claim 1, further comprising storing the address mapping table in a non-volatile memory (NVM) in a matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses storing the bad block mapping table back to NVM.).
Consider claim 9, Jo discloses the method of claim 1, wherein obtaining the address mapping table comprises generating, when a computing device loading with the memory is started, the address mapping table, and wherein the method further comprises synchronizing, before the computing device uses the memory, the address mapping table to a matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table to register storage on boot up and moving back to non-volatile before power is removed. The circuitry that performs these functions are considered part of the claimed matching and searching circuit. The map is synched with the state of the memory.).
Consider claim 10, Jo discloses the method of claim 1, wherein obtaining the memory failed row address comprises: obtaining a memory fault log of the memory; extracting a memory fault feature from the memory fault log; and performing prediction based on the memory fault feature to obtain the memory failed row address (Col. 1 lines 48-55, Col. 2 lines 23-45, Col. 3-4 lines 50-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses using re-mapping marks, re-mapping mark flags to predict whether the memory address is a failed address. The condition of a memory location is judged.).
Claims 11, 13, 14, 16, 17, 19 and 20 are the circuit claims to method claims 1-3, 5, 6, 8 and 9 above and are rejected using the same rationale.
Consider claim 12, Jo in view of Raghu et al. discloses the memory mapping circuit of claim 11, wherein the memory mapping circuit is integrated into a memory; comprising a plurality of memory chips or integrated into a central processing unit (CPU), a data processing unit (DPU), an embedded neural network processing unit (NPU), a graphics processing unit (GPU), or a tensor processing unit (TPU) (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead. Jo only discloses one memory cell array. Raghu et al.: Col. 5 line 20 discloses one or more integrated circuit chips.).
Claims 21-23 are the computer program product claims to method claims 1-3 above and are rejected using the same rationale.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 7,434,122) in view of Raghu et al. (US 8,902,658) as applied to claim 16 above, and further in view of official notice.
Consider claim 18, Jo discloses the memory mapping circuit of claim 16, however Jo does not explicitly teach that the bad block mapping register is, for example, a CAM. However, a CAM is a well-known type of memory with well-known benefits and therefore the examiner is taking official notice to its use in the system of Jo.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the register memory of Jo to be CAM memory because CAMs have fast search speeds, fixed predictable latencies and is well suited for searching tables and databases such as the bad block mapping table of Jo.
Response to Arguments
Applicant's arguments filed 8/31/2026 have been fully considered but they are not persuasive. The amendments related to the 101 rejection has resolved the 101 issue. The arguments pertaining to the new claim amendments have been addressed in the appropriate claim rejections above with the introduction of the Raghu et al. reference. As for the argument related to the official notice of claim 3, the new Raghu et al. reference teaches one or more integrated memory chips.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
