DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 21-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the term “computer-readable medium” encompasses electromagnetic signals which do not belong to any one of the four categories of invention. This term does not appear in the specification, on “computer-readable storage medium” appears. Therefore the scope cannot be determined from the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 8-11, 13, 16, 17, 19 and 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo (US 7,434,122).
Consider claim 1, Jo discloses a method comprising: obtaining a memory failed row address of a memory; obtaining an address mapping table comprising a mapping relationship between the memory failed row address and a first memory remapping row address, wherein the first memory remapping row address indicates a memory area in a reserved space of the memory; and obtaining, when an access target of the memory is the memory failed row address, the first memory remapping row address based on the mapping relationship (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead.).
Consider claim 2, Jo discloses the method of claim 1, further comprising: obtaining a memory access address from outside of the memory; performing matching on the memory access address using the address mapping table; and translating, when the memory access address matches the memory failed row address, access to the memory access address into access to the first memory remapping row address (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead.).
Consider claim 5, Jo discloses the method of claim 1, further comprising: storing the address mapping table in a volatile memory in a matching and searching circuit; writing, before the memory stops working, the address mapping table into a non-volatile memory; and loading, after the non-volatile memory starts to work, the address mapping table to the matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table to register storage on boot up and moving back to non-volatile before power is removed. The circuitry that performs these functions are considered part of the claimed matching and searching circuit.).
Consider claim 6, Jo discloses the method of claim 5, wherein in a start process of a computing device loaded with the memory, the method further comprises: reading the address mapping table from the non-volatile memory; and updating the address mapping table through memory self-check of the computing device (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table form non-volatile memory and the bad block mapping table is updated based on the state of the memory.).
Consider claim 8, Jo discloses the method of claim 1, further comprising storing the address mapping table in a non-volatile memory (NVM) in a matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses storing the bad block mapping table back to NVM.).
Consider claim 9, Jo discloses the method of claim 1, wherein obtaining the address mapping table comprises generating, when a computing device loading with the memory is started, the address mapping table, and wherein the method further comprises synchronizing, before the computing device uses the memory, the address mapping table to a matching and searching circuit (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses loading the bad block mapping table to register storage on boot up and moving back to non-volatile before power is removed. The circuitry that performs these functions are considered part of the claimed matching and searching circuit. The map is synched with the state of the memory.).
Consider claim 10, Jo discloses the method of claim 1, wherein obtaining the memory failed row address comprises: obtaining a memory fault log of the memory; extracting a memory fault feature from the memory fault log; and performing prediction based on the memory fault feature to obtain the memory failed row address (Col. 1 lines 48-55, Col. 2 lines 23-45, Col. 3-4 lines 50-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses using re-mapping marks, re-mapping mark flags to predict whether the memory address is a failed address. The condition of a memory location is judged.).
Claims 11, 13, 16, 17, 19 and 20 are the circuit claims to method claims 1, 2, 5, 6, 8 and 9 above and are rejected using the same rationale.
Claims 21 and 22 are the computer program product claims to method claims 1 and 2 above and are rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 12, 14, 18 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 7,434,122) as applied to claims 1, 11 and 16 above, and further in view of official notice.
Consider claim 3, Jo discloses the method of claim 1, wherein the memory comprises a plurality of memory chips, and wherein obtaining the first memory remapping row address comprises translating, when a failed row occurs in one of the memory chips, row addresses in the memory chips into second memory remapping row addresses comprising the failed row (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead. Jo only discloses one memory cell array).
Jo does not explicitly teach a plurality of memory chips. Jo teaches a single memory cell array. Typically a chip contains arrays of storage and therefore Jo teaches at most the equivalent of one chip and one array. However, the ability to have as much memory as is need is well-known in the art including having multiple arrays and chips. Therefore the examiner is taking official notice to having enough memory capacity to need multiple chips.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the memory of Jo to include multiple chips because having more memory allows for the storage of more data therefore improving system availability and capability.
Claim 14 is the circuit claim to method claim 3 above and is rejected using the same rationale.
Claim 23 is the computer program product claim to method claim 3 above and is rejected using the same rationale.
Consider claim 12, Jo discloses the memory mapping circuit of claim 11, wherein the memory mapping circuit is integrated into a memory; comprising a plurality of memory chips or integrated into a central processing unit (CPU), a data processing unit (DPU), an embedded neural network processing unit (NPU), a graphics processing unit (GPU), or a tensor processing unit (TPU) (Col. 2 lines 23-45, Col. 3-4 lines 50-21 and 52-67, Col. 5 lines 4-31, Col. 6 lines 40-62, Jo discloses obtaining an access request from external to the memory, this address is checked against a bad block mapping table to determine if the address is related to a bad block location (failed row address). If it is, then an address in a reserved area is used instead. Jo only discloses one memory cell array).
Jo does not explicitly teach a plurality of memory chips. Jo teaches a single memory cell array. Typically a chip contains arrays of storage and therefore Jo teaches at most the equivalent of one chip and one array. However, the ability to have as much memory as is need is well-known in the art including having multiple arrays and chips. Therefore the examiner is taking official notice to having enough memory capacity to need multiple chips.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the memory of Jo to include multiple chips because having more memory allows for the storage of more data therefore improving system availability and capability.
Consider claim 18, Jo discloses the memory mapping circuit of claim 16, however Jo does not explicitly teach that the bad block mapping register is, for example, a CAM. However, a CAM is a well-known type of memory with well-known benefits and therefore the examiner is taking official notice to its use in the system of Jo.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the register memory of Jo to be CAM memory because CAMs have fast search speeds, fixed predictable latencies and is well suited for searching tables and databases such as the bad block mapping table of Jo.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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