Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5-7 and 16-18 are objected to because of the following informalities: the recitation “at least one fourth differential inverting amplifier” is not clear because amplifier can’t have a fraction, 1/4. Appropriate correction is required. The examiner interprets as fourth differential inverting amplifier.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP3769718 (cited by the applicant, in IDS filed on 3/25/2026, Extended European Search Report).
Regarding claim 1, JP3769718 discloses a ring oscillator (FIG 1), wherein the ring oscillator comprises at least three (FIG 1 shows four) differential inverting amplifiers (12a-12n) that are coupled in a ring, each differential inverting amplifier of the at least three differential inverting amplifiers comprises a first input end (positive +) and a second input end (negative -) that are differential, and a first output end and a second output end that are differential, and wherein the first output end and the second output end of the each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier; and the at least three differential inverting amplifiers comprise a first differential inverting amplifier (12b), a first input end (+) of the first differential inverting amplifier is coupled to (via 17a, 17b) a first output end (+) of the first differential inverting amplifier, a second input end (-) of the first differential inverting amplifier (12b) is coupled to (via 18a, 18b) a second output end (-) of the first differential inverting amplifier (12b), a polarity of the first input end (+) and a polarity of the first output end (+) are a first polarity (+), a polarity of the second input end (-) and a polarity of the second output end (-) are a second polarity (-), and the first polarity (+) is opposite to the second polarity (-).
Regarding claim 2|1, JP3769718 discloses the ring oscillator wherein the at least three differential inverting amplifiers further comprise a second differential inverting amplifier (12c) and a third differential inverting amplifier (12a), and the first differential inverting amplifier (12b) is coupled between the second differential inverting amplifier (12c) and the third differential inverting amplifier (12a).
Regarding claim 3|1, JP3769718 discloses the ring oscillator wherein the ring oscillator further comprises a first switch (17a, 17b) and a second switch (18a, 18b); and the first switch is coupled between the first input end (+) of the first differential inverting amplifier (12b) and the first output end (+) of the first differential inverting amplifier (12b), and the second switch (18a, 18b) is coupled between the second input end (-) of the first differential inverting amplifier (12b) and the second output end (-) of the first differential inverting amplifier (12b).
Regarding claim 4|3|1, JP3769718 discloses the ring oscillator wherein the ring oscillator is controlled to operate in a low phase noise mode or an anti-interference mode by switching the first switch and the second switch (the structure of JP3769718 inherently provides such functional feature because of the identical structure as recited in the claim).
Regarding claim 5|2|1, JP3769718 discloses the ring oscillator wherein the at least three differential inverting amplifiers further comprise at least one fourth differential inverting amplifier (12d), the at least one fourth differential inverting amplifier (12d) is coupled between the second differential inverting amplifier (12c) and the third differential inverting amplifier (12a)(in a ring configuration), a first input end (+) of the at least one fourth differential inverting amplifier (12d) is coupled to a first output end (+) of the at least one fourth differential inverting amplifier, a second input end (-) of the at least one fourth differential inverting amplifier is coupled to a second output end (-) of the at least one fourth differential inverting amplifier, a polarity (+) of the first input end of the at least one fourth differential inverting amplifier and a polarity (-) of the first output end of the at least one fourth differential inverting amplifier are the first polarity, and a polarity of the second input end of the at least one fourth differential inverting amplifier and a polarity of the second output end of the at least one fourth differential inverting amplifier are the second polarity.
Regarding claim 6|5|2|1, JP3769718 discloses the ring oscillator wherein the ring oscillator further comprises a third switch (17c, 17d) and a fourth switch (18c, 18d); and the third switch is coupled between the first input end of the at least one fourth differential inverting amplifier and the first output end of the at least one fourth differential inverting amplifier, and the fourth switch is coupled between the second input end of the at least one fourth differential inverting amplifier and the second output end of the at least one fourth differential inverting amplifier.
Regarding claim 7|6|5|2|1, JP3769718 discloses the ring oscillator wherein the ring oscillator is controlled to operate in a low phase noise mode or an anti-interference mode by turning off a first switch and a second switch and switching the third switch and the fourth switch; or the ring oscillator is controlled to operate in the low phase noise mode or the anti-interference mode by turning off the third switch and the fourth switch and switching the first switch and the second switch (the structure of JP3769718 inherently provides such functional feature because of the identical structure as recited in the claim).
Regarding claim 8|1, JP3769718 discloses the ring oscillator wherein only one differential inverting amplifier in the at least three differential inverting amplifiers is reversely coupled to an adjacent differential inverting amplifier, and all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are in-phase coupled to adjacent differential inverting amplifiers (transmission gates 17 and 18 are capable of configuring such coupling of differential inverting amplifiers as recited).
Regarding claim 9|1, JP3769718 discloses the ring oscillator (FIG 1) wherein only one differential inverting amplifier (12n) in the at least three differential inverting amplifiers is in-phase coupled to an adjacent differential inverting amplifier, and all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are reversely coupled to adjacent differential inverting amplifiers.
Regarding claim 10, JP3769718 discloses a phase locked loop circuit (¶[0001]), wherein the phase locked loop circuit comprises a phase detector, a filter, and a ring oscillator, the phase detector is configured to: obtain a phase difference signal, and convert the phase difference signal into a voltage signal, the filter is configured to filter the voltage signal, and the ring oscillator is configured to output a local carrier signal based on the filtered voltage signal (PLL intrinsic functional property) ; wherein the ring oscillator (FIG 1) comprises at least three differential inverting amplifiers that are coupled in a ring, each differential inverting amplifier of the at least three differential inverting amplifiers comprises a first input end and a second input end that are differential, and a first output end and a second output end that are differential, and wherein the first output end and the second output end of the each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier; and the at least three differential inverting amplifiers comprise a first differential inverting amplifier, a first input end of the first differential inverting amplifier is coupled to a first output end of the first differential inverting amplifier, a second input end of the first differential inverting amplifier is coupled to a second output end of the first differential inverting amplifier, a polarity of the first input end and a polarity of the first output end are a first polarity, a polarity of the second input end and a polarity of the second output end are a second polarity, and the first polarity is opposite to the second polarity (see the claim 1 rejection).
Regarding claim 11, JP3769718 discloses a communication apparatus (¶[0001]), wherein the communication apparatus comprises a phase locked loop circuit, and the phase locked loop circuit comprises a ring oscillator; the ring oscillator (FIG 1) comprises at least three differential inverting amplifiers that are coupled in a ring, each differential inverting amplifier of the at least three differential inverting amplifiers comprises a first input end and a second input end that are differential, and a first output end and a second output end that are differential, and wherein the first output end and the second output end of the each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier; and the at least three differential inverting amplifiers comprise a first differential inverting amplifier, a first input end of the first differential inverting amplifier is coupled to a first output end of the first differential inverting amplifier, a second input end of the first differential inverting amplifier is coupled to a second output end of the first differential inverting amplifier, a polarity of the first input end and a polarity of the first output end are a first polarity, a polarity of the second input end and a polarity of the second output end are a second polarity, and the first polarity is opposite to the second polarity (see the claim 1 rejection).
Regarding claim 12|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the communication apparatus further comprises a radio frequency transceiver, the phase locked loop circuit is integrated into the radio frequency transceiver, and the phase locked loop circuit is configured to provide a local carrier signal for the radio frequency transceiver (¶[0001]).
Regarding claim 13|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the at least three differential inverting amplifiers further comprise a second differential inverting amplifier and a third differential inverting amplifier, and the first differential inverting amplifier is coupled between the second differential inverting amplifier and the third differential inverting amplifier (see the claim 2 rejection).
Regarding claim 14|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the ring oscillator further comprises a first switch and a second switch; and the first switch is coupled between the first input end of the first differential inverting amplifier and the first output end of the first differential inverting amplifier, and the second switch is coupled between the second input end of the first differential inverting amplifier and the second output end of the first differential inverting amplifier (see the claim 3 rejection).
Regarding claim 15|14|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the ring oscillator is controlled to operate in a low phase noise mode or an anti-interference mode by switching the first switch and the second switch (see the claim 4 rejection).
Regarding claim 16|13|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the at least three differential inverting amplifiers further comprise at least one fourth differential inverting amplifier, the at least one fourth differential inverting amplifier is coupled between the second differential inverting amplifier and the third differential inverting amplifier, a first input end of the at least one fourth differential inverting amplifier is coupled to a first output end of the at least one fourth differential inverting amplifier, a second input end of the at least one fourth differential inverting amplifier is coupled to a second output end of the at least one fourth differential inverting amplifier, a polarity of the first input end of the at least one fourth differential inverting amplifier and a polarity of the first output end of the at least one fourth differential inverting amplifier are the first polarity, and a polarity of the second input end of the at least one fourth differential inverting amplifier and a polarity of the second output end of the at least one fourth differential inverting amplifier are the second polarity (see the claim 5 rejection).
Regarding claim 17|16|13|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the ring oscillator further comprises a third switch and a fourth switch; and the third switch is coupled between the first input end of the at least one fourth differential inverting amplifier and the first output end of the at least one fourth differential inverting amplifier, and the fourth switch is coupled between the second input end of the at least one fourth differential inverting amplifier and the second output end of the at least one fourth differential inverting amplifier (see the claim 6 rejection).
Regarding claim 18|17|16|13|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein the ring oscillator is controlled to operate in a low phase noise mode or an anti-interference mode by turning off a first switch and a second switch and switching the third switch and the fourth switch; or the ring oscillator is controlled to operate in the low phase noise mode or the anti-interference mode by turning off the third switch and the fourth switch and switching the first switch and the second switch (see the claim 7 rejection).
Regarding claim 19|11, JP3769718 discloses the communication apparatus according (¶[0001], FIG 1) wherein only one differential inverting amplifier in the at least three differential inverting amplifiers is reversely coupled to an adjacent differential inverting amplifier, and all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are in-phase coupled to adjacent differential inverting amplifiers (see the claim 8 rejection).
Regarding claim 20|11, JP3769718 discloses the communication apparatus (¶[0001], FIG 1) wherein only one differential inverting amplifier in the at least three differential inverting amplifiers is in-phase coupled to an adjacent differential inverting amplifier, and all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are reversely coupled to adjacent differential inverting amplifiers (see the claim 9 rejection).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chi (US 5,239,274) discloses a differential ring oscillator showing three inverters and four inverters.
Martin (US 5180994) discloses a differential ring oscillator having four inverting stages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/ Primary Examiner, Art Unit 2836
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