DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 18 of U.S. Patent No. 12,352,621. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claim 1 discloses all of the features of claim 14 and 18, including precharging a first capacitor via a preset circuit having a second capacitor, the first capacitor coupled to an operational amplifier and the preset circuit, the preset circuit coupled to a first voltage node for carrying a first voltage equal to a preset voltage multiplied by a coefficient, the second capacitor having a capacitance equal to a capacitance of the first capacitor divided by the coefficient, performing an integration phase to obtain a voltage level at the first capacitor, and discharging the first capacitor after the integration phase is complete.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 18 of U.S. Patent No. 12,352,621 in view of U.S. Patent Publication No. 2022/0299362 ("Adusumalli"). Adusumalli discloses an ambient light sensor (206, Fig. 3A, paragraph [0029]), and it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the two circuits in order to obtain more accurate ambient light measurements by suppressing the amplifiers’ offset as well as parasitic capacitances.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2022/0357374 ("Gan") in view of U.S. Patent No. 4,633,425 ("Senderowicz").
Regarding claim 1, Gan discloses the method for operating a circuit comprising:
precharging a first capacitor (Cfb1 or Cfb2, Fig. 5, paragraph [0046]) of the circuit via a second capacitor (either C1, C2, Fig. 5, paragraph [0045]) of the circuit;
the first capacitor (Cfb1 or Cfb2, Fig. 5) coupled to an operational amplifier (FDA, Fig. 5, under the broadest reasonable interpretation, a fully differential amplifier is a type of operational amplifier) of the circuit,
the first capacitor (Cfb1 via N3 or Cfb2 via N4, Fig. 5) coupled to an output of a preset circuit (160, Fig. 5), the preset circuit (160, Fig 5) having an input coupled to a first voltage node (do1, do2 of 120, Fig. 5) for carrying a first voltage (Va1, Va2, Fig. 5) equal to a preset voltage multiplied by a coefficient (voltage at terminals o1, o2 become amplitude voltage at terminals do1, do2, Fig. 5, paragraph [0025]), the preset circuit (160, Fig. 5) comprising the second capacitor (either C1, C2, Fig. 5);
performing an integration phase where a voltage level is obtained at the first capacitor (integrated voltage, paragraphs [0039], [0047]-[0048]); and
discharging the first capacitor after the integration phase is complete (Fig. 4, paragraph [0047]).
Gan does not explicitly disclose that the second capacitor has a capacitance equal to a capacitance of the first capacitor divided by the coefficient.
However, Senderowicz discloses that the second capacitor (either capacitor C within 22, Fig. 1) has a capacitance equal to a capacitance of the first capacitor (32, Fig. 1) divided by the coefficient (see α, Fig. 2, and col. 3, lines 33-35).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to choose the specific capacitance values for the capacitors in the circuit as disclosed by Senderowicz in the device of Gan in order to obtain the desired circuit output effect.
Regarding claim 2, Gan in view of Senderowicz discloses the method of claim 1, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) includes a first electrode and a second electrode (inherent, see electrodes in Fig. 5), wherein the first electrode is coupled to an inverting input of the operational amplifier (inverting input of FDA, Fig. 5), and wherein the second electrode is coupled to a non-inverting output of the operational amplifier (non-inverting output of FDA, Fig. 5, paragraph [0035]).
Regarding claim 3, Gan in view of Senderowicz discloses the method of claim 2, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) is coupled to the operational amplifier (FDA, Fig. 5) via a compensation circuit (CC1, CC2, Fig. 5).
Regarding claim 4, Gan in view of Senderowicz discloses the method of claim 3, and Gan further discloses that the compensation circuit (CC1, CC2, Fig. 5) comprises an input circuit (CC1, Fig. 5) and an output circuit (CC2, Fig. 5) coupled to the operational amplifier (FDA, Fig. 5).
Regarding claim 5, Gan in view of Senderowicz discloses the method of claim 4, and Gan further discloses compensating, by the compensation circuit (CC1, CC2, Fig. 5), for an offset voltage of the operational amplifier (paragraph [0051]-[0052]).
Regarding claim 6, Gan in view of Senderowicz discloses the method of claim 5, further comprising delivering, by the compensation circuit (CC1, CC2, Fig. 5), a square pulse signal having an amplitude equal to the amplitude of the offset voltage of the operational amplifier (Gan discloses the same compensation circuit structure as claimed, it therefore functions in the same manner and delivers a square pulse signal having an amplitude equal to the amplitude of the offset voltage of the operational amplifier, see Fig. 4 and paragraph [0052]).
Regarding claim 8, Gan discloses a circuit, comprising:
an operational amplifier (FDA, Fig. 5, under the broadest reasonable interpretation, a fully differential amplifier is a type of operational amplifier);
a first capacitor (Cfb1 or Cfb2, Fig. 5) coupled to the operational amplifier (FDA, Fig. 5); and
a preset circuit (160, Fig. 5) having an input coupled to a first voltage node (do1, do2 of 120, Fig. 5) and an output coupled to the first capacitor (Cfb1 or Cfb2, Fig. 5), the first voltage node (do1, do2 of 120, Fig. 5) configured to carry a first voltage (Va1, Va2, Fig. 5) equal to a preset voltage multiplied by a coefficient (voltage at terminals o1, o2 become amplitude voltage at terminals do1, do2, Fig. 5, paragraph [0025]), the preset circuit comprising a second capacitor (either C1, C2, Fig. 5), the preset circuit configured to pre-charge the first capacitor (Cfb1 or Cfb2, Fig. 5) via the second capacitor (either C1, C2, Fig. 5), wherein the circuit is configured to perform an integration phase to obtain a voltage level (integrated voltage, paragraphs [0039], [0047]-[0048]) at the first capacitor (Cfb1 or Cfb2, Fig. 5) and discharge the first capacitor (Cfb1 or Cfb2, Fig. 5) after the completion of the integration phase (Fig. 4, paragraph [0047]).
Gan does not explicitly disclose that the second capacitor has a capacitance equal to a capacitance of the first capacitor divided by the coefficient.
However, Senderowicz discloses that the second capacitor (either capacitor C within 22, Fig. 1) has a capacitance equal to a capacitance of the first capacitor (32, Fig. 1) divided by the coefficient (see α, Fig. 2, and col. 3, lines 33-35).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to choose the specific capacitance values for the capacitors in the circuit as disclosed by Senderowicz in the device of Gan in order to obtain the desired circuit output effect.
Regarding claim 9, Gan in view of Senderowicz discloses the circuit of claim 8, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) includes a first electrode and a second electrode (inherent, see electrodes in Fig. 5), wherein the first electrode is coupled to an inverting input of the operational amplifier (inverting input of FDA, Fig. 5), and wherein the second electrode is coupled to a non-inverting output of the operational amplifier (non-inverting output of FDA, Fig. 5, paragraph [0035]).
Regarding claim 10, Gan in view of Senderowicz discloses the circuit of claim 9, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) is coupled to the operational amplifier (FDA, Fig. 5) via a compensation circuit (CC1, CC2, Fig. 5).
Regarding claim 11, Gan in view of Senderowicz discloses the circuit of claim 10, and Gan further discloses that the compensation circuit (CC1, CC2, Fig. 5) comprises an input circuit (CC1, Fig. 5) and an output circuit (CC2, Fig. 5) coupled to the operational amplifier (FDA, Fig. 5).
Regarding claim 12, Gan in view of Senderowicz discloses the circuit of claim 11, and Gan further discloses that the compensation circuit (CC1, CC2, Fig. 5) is configured to compensate for an offset voltage of the operational amplifier (paragraph [0051]-[0052]).
Regarding claim 13, Gan in view of Senderowicz discloses the circuit of claim 12, wherein the compensation circuit is configured to deliver a square pulse signal having an amplitude equal to an amplitude of the offset voltage of the operational amplifier (Gan discloses the same compensation circuit structure as claimed, it therefore functions in the same manner and delivers a square pulse signal having an amplitude equal to the amplitude of the offset voltage of the operational amplifier, see Fig. 4 and paragraph [0052]).
Claims 7 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gan in view of Senderowicz further in view of U.S. Patent Publication No. 2022/0299362 ("Adusumalli")
Regarding claims 7 and 14, Gan in view of Senderowicz discloses the method of claim 2 and circuit of claim 9, but does not disclose that the first electrode of the first capacitor is coupled to an ambient light sensor.
However, Adusumulli discloses that the first electrode of the first capacitor (224, Fig. 3A) is coupled to an ambient light sensor (206, Fig. 3A, paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include a photodiode as an ambient light sensor as disclosed by Adusumalli in order to obtain more accurate ambient light measurements as required for any given application.
Regarding claim 15, Gan discloses an ambient light measurement system, comprising:
a readout circuit comprising:
an operational amplifier (FDA, Fig. 5, under the broadest reasonable interpretation, a fully differential amplifier is a type of operational amplifier), a first capacitor (Cfb1 or Cfb2, Fig. 5) coupled to the operational amplifier (FDA, Fig. 5), and a preset circuit (160, Fig. 5) having an input coupled to a first voltage node (do1, do2 of 120, Fig. 5) and an output coupled to the first capacitor (Cfb1 or Cfb2, Fig. 5), the first voltage node (do1, do2 of 120, Fig. 5) configured to carry a first voltage (Va1, Va2, Fig. 5) equal to a preset voltage multiplied by a coefficient (voltage at terminals o1, o2 become amplitude voltage at terminals do1, do2, Fig. 5, paragraph [0025]), the preset circuit comprising a second capacitor (either C1, C2, Fig. 5), the preset circuit configured to pre-charge the first capacitor (Cfb1 or Cfb2, Fig. 5) via the second capacitor (either C1, C2, Fig. 5), wherein the readout circuit is configured to perform an integration phase to obtain a voltage level (integrated voltage, paragraphs [0039], [0047]-[0048]) at the first capacitor (Cfb1 or Cfb2, Fig. 5) and discharge the first capacitor (Cfb1 or Cfb2, Fig. 5) after the completion of the integration phase (Fig. 4, paragraph [0047]).
Gan does not disclose an ambient light sensor coupled to the readout circuit, nor that the second capacitor has a capacitance equal to a capacitance of the first capacitor divided by the coefficient.
However, Senderowicz discloses that the second capacitor (either capacitor C within 22, Fig. 1) has a capacitance equal to a capacitance of the first capacitor (32, Fig. 1) divided by the coefficient (see α, Fig. 2, and col. 3, lines 33-35).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to choose the specific capacitance values for the capacitors in the circuit as disclosed by Senderowicz in the device of Gan in order to obtain the desired circuit output effect.
Gan in view of Senderowicz does not disclose an ambient light sensor.
However, Adusumulli discloses a readout circuit (see Fig. 3A) is coupled to an ambient light sensor (206, Fig. 3A, paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include a photodiode as an ambient light sensor as disclosed by Adusumalli in order to obtain more accurate ambient light measurements as required for any given application.
Regarding claim 16, Gan in view of Senderowicz and Adusumulli discloses the ambient light measurement system of claim 15, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) includes a first electrode and a second electrode (inherent, see electrodes in Fig. 5), wherein the first electrode is coupled to an inverting input of the operational amplifier (inverting input of FDA, Fig. 5), and wherein the second electrode is coupled to a non-inverting output of the operational amplifier (non-inverting output of FDA, Fig. 5, paragraph [0035]).
Regarding claim 17, Gan in view of Senderowicz and Adusumulli discloses the ambient light measurement system of claim 16, and Gan further discloses that the first capacitor (Cfb2, Fig. 5) is coupled to the operational amplifier (FDA, Fig. 5) via a compensation circuit (CC1, CC2, Fig. 5).
Regarding claim 18, Gan in view of Senderowicz and Adusumulli discloses the ambient light measurement system of claim 17, and Gan further discloses that the compensation circuit (CC1, CC2, Fig. 5) comprises an input circuit (CC1, Fig. 5) and an output circuit (CC2, Fig. 5) coupled to the operational amplifier (FDA, Fig. 5).
Regarding claim 19, Gan in view of Senderowicz and Adusumulli discloses the ambient light measurement system of claim 18, and Gan further discloses that the compensation circuit (CC1, CC2, Fig. 5) is configured to compensate for an offset voltage of the operational amplifier (paragraph [0051]-[0052]).
Regarding claim 20, Gan in view of Senderowicz and Adusumulli discloses the ambient light measurement system of claim 19, wherein the compensation circuit is configured to deliver a square pulse signal having an amplitude equal to an amplitude of the offset voltage of the operational amplifier (Gan discloses the same compensation circuit structure as claimed, it therefore functions in the same manner and delivers a square pulse signal having an amplitude equal to the amplitude of the offset voltage of the operational amplifier, see Fig. 4 and paragraph [0052]).
Conclusion
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/MONICA T TABA/Examiner, Art Unit 2878
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