DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed provisional application 63/658598 filed on 06/11/2024 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9-16, and 19-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US2021/0318820) hereinafter Jin in view of Cheng (US2025/0335125), hereinafter Cheng.
Regarding claims 1, 11, and 21, taking claim 1 as exemplary, Jin teaches a memory system, comprising:
one or more memory devices (Jin, [0026], data storage device 10); and
processing circuitry (Jin, [0041], the controller 110 may include a processor 111) coupled with the one or more memory devices (Jin, [0042], The processor 111 may be configured to transmit various control information, which are required for performing a read or write operation on the storage 120; Fig.1) and configured to cause the memory system to:
store first data to a first portion of a write buffer of the memory system in response to receiving a first write command (Jin, [0049], The ZNS manager 20 may temporarily store (buffer) write data in at least one sub buffer zone, which is allocated as a portion of the buffer zone 1201 of FIG. 2, in response to a write request of the host), wherein the write buffer comprises the first portion that is associated with a first set of sequential logical addresses and a second portion that is associated with a second set of sequential logical addresses (Jin, [0056], When the write request is determined to be the sequential data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone);
store second data to the second portion of the write buffer in response to receiving a second write command (Jin, [0056], When the write request is determined to be the sequential data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone so that the write data is written); and
transfer, from the second portion of the write buffer, the second data to a first set of multiple-level memory cells having sequential physical addresses in accordance with a quantity of data stored to the second portion of the write buffer satisfying a threshold value (Jin, [0039], the data zone 1203 may be programmed according to the XLC method which stores multi-bit data, [0064], the migrator 205 may allocate or open a ZNS corresponding to the length of the write data in the data zone 1203 shown in FIG. 2 when all the segments of the write data are buffered in the allocated sub buffer zone and thus the allocated sub buffer zone is closed. Then, the migrator 205 may migrate the segments of the write data that have been buffered in the closed sub buffer zone to the ZNS; [0073]).
Jin teaches transferring data from a buffer zone to a data zone, nevertheless, Jin does not explicitly teach the multi-level memory cells having sequential physical addresses, as claimed.
However, Jin in view of Cheng teaches wherein the write buffer comprises the first portion that is associated with a first set of sequential logical addresses and a second portion that is associated with a second set of sequential logical addresses (Cheng, [0089], The logical addresses corresponding to each zone are contiguous; [0098]; Fig.7; Jin, [0056], When the write request is determined to be the sequential data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone so that the write data is written according to a second write (or program) method)
a first set of multiple-level memory cells having sequential physical addresses (Cheng, [0024], the storage area includes multiple second zones which include contiguous physical addresses).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin to incorporate teachings of Cheng to associate a first buffer subzone with a first set of sequential logical addresses and a second buffer subzone with a second set of sequential logical addresses. The data zone comprises a set of multiple-level memory cells having sequential physical addresses. A person of ordinary skill in the art would have been motivated to combine the teachings of the Jin with Cheng because it improves efficiency of the storage system disclosed in Jin by writing data sequentially using contiguous logical and/or physical addresses.
Claims 11 and 21 have similar limitations as claim 1 and they are rejected for the similar reasons.
Regarding claims 2, 12, and 22, taking claim 2 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim 1, wherein the write buffer comprises a third portion that is associated with a third set of random logical addresses, and the processing circuitry is further configured to cause the memory system to: store third data to the third portion of the write buffer in response to receiving a third write command, wherein the third set of random logical addresses comprises one or more non-sequential logical addresses (Jin, [0056], when the write request is determined to be the random data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone so that the write data is written according to a first write (or program) method).
Claims 12 and 22 have similar limitations as claim 2 and they are rejected for the similar reasons.
Regarding claims 3, 13, and 23, taking claim 3 as exemplary, the combination of Jin teaches all the features with respect to claim 2 as outlined above. The combination of Jin further teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: partition, by the memory system, the write buffer into a plurality of portions comprising at least the first portion, the second portion, and the third portion (Jin, [0056], allocate at least one sub buffer zone in the buffer zone 1201; Cheng, [0098], the buffer area 105 may include multiple first zones, taking three first zones as an example, namely first zones A1 to A3).
Claims 13 and 23 have similar limitations as claim 3 and they are rejected for the similar reasons.
Regarding claim 4, 14, and 24, taking claim 4 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: transfer, from the first portion of the write buffer, the first data to a second set of multiple-level memory cells having sequential physical addresses in accordance with a second quantity of data stored to the first portion of the write buffer satisfying the threshold value (Cheng, [0016], the storage area includes multiple second zones which include contiguous physical addresses; [0098], When the buffer area 105 is written fully or needs to be cleared to provide buffer space for the next write operation request, the data in the buffer area 105 is sequentially written into the storage area 107, and the logical address-physical address mapping table is updated; [0097], performs a program operation such as the TLC on the memory cells in the storage area 107).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin to incorporate teachings of Cheng to close a buffer zone/subzone when the buffer zone/subzone is full and the data temporally stored in the buffer zone/subzone is flushed into a data zone. A person of ordinary skill in the art would have been motivated to combine the teachings of the Jin with Cheng because it improves efficiency of the storage system disclosed in Jin by writing data sequentially using contiguous logical and/or physical addresses.
Claims 14 and 24 have similar limitations as claim 4 and they are rejected for the similar reasons.
Regarding claim 5, 15, and 25, taking claim 5 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim 1, wherein the threshold value is associated with a storage capacity of the second portion of the write buffer (Jin, [0049], When the one or more sub buffer zones used for buffering the write data are closed, the ZNS manager 20 may open a ZNS corresponding to a size of the write data in the data zone 1203, migrate the one or more segments of the write data stored in the one or more sub buffer zones of the buffer zone 1201 to the opened ZNS in the data zone 1203; Cheng, [0094], The buffer area 105 has a faster operation rate than that of other non-buffer areas (e.g., the storage area 107), e.g., a faster program (write) rate, the data is first programmed and written into the buffer area 105, and then written into other non-buffer areas after the buffer area 105 is fully written, and the relevant data in the buffer area 105 is erased after the data is written into the non-buffer area to release the buffer space for the next write).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin to incorporate teachings of Cheng to close a buffer zone/subzone when the buffer zone/subzone is full and the data temporally stored in the buffer zone/subzone is flushed into a data zone. A person of ordinary skill in the art would have been motivated to combine the teachings of the Jin with Cheng because it improves efficiency of the storage system disclosed in Jin by writing data sequentially using contiguous logical and/or physical addresses.
Claims 15 and 25 have similar limitations as claim 5 and they are rejected for the similar reasons.
Regarding claims 6 and 16, taking claim 6 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim1,wherein the processing circuitry is further configured to cause the memory system to:
determine that the first data comprises sequential data in response to receiving the first write command (Jin, [0055], The workload analyzer 201 may determine whether or not a write request of the host is a random data write request or a sequential data write request in response to the write request of the host.), wherein storing the first data to the first portion is in response to determining that the first data comprises sequential data (Jin, [0056], When the write request is determined to be the sequential data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone ); and
determine that the second data comprises sequential data in response to receiving the second write command (Jin, [0055], The workload analyzer 201 may determine whether or not a write request of the host is a random data write request or a sequential data write request in response to the write request of the host.), wherein storing the second data to the second portion is in response to determining that the second data comprises sequential data (Jin, [0056], When the write request is determined to be the sequential data write request as the workload determination result, the buffer zone manager 203 may allocate a portion of the buffer zone 1201 as the at least one sub buffer zone ).
Claim 16 has similar limitations as claim 6 and is rejected for the similar reasons.
Regarding claims 9 and 19, taking claim 9 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim 1, wherein the write buffer comprises a plurality of single-level memory cells (Jin, [0038], the buffer zone 1201 may be programmed according to an SLC method which stores 1-bit data in one memory cell; Cheng, [0094], the buffer area 105 may include multiple first memory cells in which data is stored in a single-level mode, e.g., SLC ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin to incorporate teachings of Cheng use SLC memory cells for buffer memory. A person of ordinary skill in the art would have been motivated to combine the teachings of the Jin with Cheng because it improves performance of the storage system disclosed in Jin by storing data in single-level mode for faster access in order to reduce latency.
Claim 19 has similar limitations as claim 9 and is rejected for the similar reasons.
Regarding claims 10 and 20, taking claim 10 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin further teaches the memory system of claim 1, wherein the first set of multiple-level memory cells comprises one or more triple-level memory cells (Cheng, [0092], the storage area 107 includes multiple second memory cells (multiple level cell, e.g., TLC) in which data is stored in a multi-level mode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin to incorporate teachings of Cheng use TLC memory cells for data zone/storage area. A person of ordinary skill in the art would have been motivated to combine the teachings of the Jin with Cheng because it improves efficiency of the storage system disclosed in Jin by storing data in multi-level mode in order to reduce storage space needed.
Claim 19 has similar limitations as claim 9 and is rejected for the similar reasons.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Jin and Cheng as applied to claims 1 and 11 respectively above, and further in view of Park et al. (US2019/0294376), hereinafter Park.
Regarding claims 7 and 17, taking claim 7 as exemplary, the combination of Jin teaches all the features with respect to claim 6 as outlined above. The combination of Jin does not explicitly teach the memory system of claim 6, wherein: determining that the first data comprises sequential data is in accordance with the first write command comprising a bit indicating that the first data comprises sequential data; and determining that the second data comprises sequential data is in accordance with the second write command comprising a bit indicating that the second data comprises sequential data, as claimed.
However, the combination of Jin in view of Park teaches the memory system of claim 6, wherein: determining that the first data comprises sequential data is in accordance with the first write command comprising a bit indicating that the first data comprises sequential data; and determining that the second data comprises sequential data is in accordance with the second write command comprising a bit indicating that the second data comprises sequential data (Park, [0053], a command CMD may include a plurality of bits, and the plurality of bits may include an operation code OC (or a command index), an address AD, a data size DS, and flag bits FBS [0055], The flag bits FBS may include various mode information. In an embodiment, when the command CMD is a write command CMDW, at least one bit of the flag bits FBS may be a sequential write flag bit indicating whether write data corresponding to the write command CMDW is sequential data).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified combination of Jin to incorporate teachings of Park to include a flag bit in a write command to indicate whether write data associated to the write command is sequential data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Jin with Park because it improves efficiency of the storage system disclosed in the combination of Jin by allowing a host to communicate to a storage device the type of data in a write command.
Claim 17 has similar limitations as claim 7 and is rejected for the similar reasons.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Jin and Cheng as applied to claims 1 and 11 respectively above, and further in view of Marakala et al. (US2024/0419561), hereinafter Marakala.
Regarding claims 8 and 18, taking claim 8 as exemplary, the combination of Jin teaches all the features with respect to claim 1 as outlined above. The combination of Jin does not explicitly teach the memory system of claim 1, wherein the first data is associated with a first application and the second data is associated with a second application different than the first application, wherein the first application and the second application are executed concurrently, as claimed.
However, the combination of Jin in view of Marakala teaches the memory system of claim 1, wherein the first data is associated with a first application and the second data is associated with a second application different than the first application, wherein the first application and the second application are executed concurrently (Marakala, [0176], The storage systems described above may support the serialized or simultaneous execution of artificial intelligence applications, machine learning applications, data analytics applications; [0188], each zone may be mapped, for example, to a separate application such that functions like wear levelling and garbage collection could be performed on a per-zone or per-application basis ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Jin to incorporate teachings of Marakala to map a separate application to a zone/subzone and applications are executed simultaneously. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Jin with Marakala because it improves efficiency and performance of the storage system disclosed in the combination of Jin by executing a plurality of applications in parallel.
Claim 18 has similar limitations as claim 8 and is rejected for the similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jin et al. (US2021/0056023) teaches a buffer memory is partitioned into a plurality of areas and each area is mapped to a specific zone which is also mapped to a specific application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NANCI N WONG/Primary Examiner, Art Unit 2137
Prosecution Insights