Prosecution Insights
Last updated: October 01, 2026
Application No. 19/222,888

ACCESS PATTERN TRACKING

Non-Final OA §102
Filed
May 29, 2025
Priority
Jun 11, 2024 — provisional 63/658,710
Examiner
GRULLON, FRANCISCO A
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
354 granted / 403 resolved
+27.8% vs TC avg
Minimal -1% lift
Without
With
+-1.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
6 currently pending
Career history
418
Total Applications
across all art units

Statute-Specific Performance

§101
7.6%
-32.4% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 403 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Note It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Claim Status Applicant’s election without traverse of claims 1-13, 19-24, 29, and 30 in the reply filed on 09 July 2026 is acknowledged. Claims 14-18 and 25-28 are withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 13, 19-20, and 29-30 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim (US 20160098201 A1). Referring to claims 1, 19, and 29, taking claim 1 as exemplary, Kim teaches A method at a memory system, comprising: receiving, from a host system, an access request associated with accessing first data stored in a memory of a plurality of memories of the memory system; ([Kim 0012-0014, 0035, 0038, 0126, Fig. 1] The data storage device 10 may store the data provided from an external device (not shown) (i.e. host), in response to a write request from the external device. Also, the data storage device 10 may provide stored data to the external device, in response to a read request from the external device. a data storage device may include a storage medium including a plurality of nonvolatile memory apparatuses. The processor 110 may generate an access command for accessing a target region of the nonvolatile memory apparatus 200, for example, a write command or a read command, and may provide the generated access command to the nonvolatile memory apparatus 200. The processor 110 may drive a software program for controlling the operation of the data storage device 10, on the memory 120. At step S410, the processor 410 may receive an access request, for example, a read request, from an external device (i.e. host).) calculating, at the memory based on receiving the access request, a hash value based on a page index indicated in the access request; ([Kim 0011, 0068-0071, Fig. 6] a method for operating a data storage device may include mapping an address of a target region, which is access-requested, into a first hash value of a plurality of first hash values based on a first hash function. The hashing unit 115 may calculate the hash values HV that correspond to the first to eighth pages P1 to P8 of FIG. 2. The hashing unit 115 may map the addresses ADD of the first to eighth pages P1 to P8 into a corresponding one of the hash values HV based on a hash function. For example, when the first page P1 is accessed as the target region by the access command, the hashing unit 115 may map the address ADD_P1 of the first page P1 into the common hash value ‘2’.) incrementing, based on the hash value, a counter of a plurality of counters, the counter being associated with the hash value; ([Kim abstract, 0011, 0040-0043, 0070-0072, Fig. 6] updating a first access count indexed by the first hash value in a first access count table that includes a plurality of first access counts indexed by the plurality of first hash values. The processor 110 may manage the access count table 125 on the memory 120. The access count table 125 may include one or more values of access counts each of which represents how many times a corresponding region of the nonvolatile memory apparatus 200 is accessed. Each time a target region of the nonvolatile memory apparatus 200 is accessed, the processor 110 may calculate a hash value HV corresponding to the target region of the nonvolatile memory apparatus 200, and may update an access count that is indexed by the calculated hash value HV, in the access count table 125.) and indicating, based on incrementing the counter, an access pattern associated with accessing data in the memory to the host system ([Flynn 0011, 0013, 0043, 0067-0069, Fig. 4, 6] updating an access request count based on an access request. a data storage device may include a storage medium including a plurality of nonvolatile memory apparatuses, and a controller suitable for updating a first access count and a second access count when accessing a target region of the storage medium, wherein the first access count corresponds to a plurality of first unit regions which include the target region and correspond to a common hash value (i.e. pattern) based on a hash function, and the second access count corresponds to a super block which includes the target region and second unit regions of the respective nonvolatile memory apparatuses. The processor 110 may manage the plurality of regions in the integrated way through a common hash value. Under the integrated management, the hashing unit 115 may map the addresses of the plurality of regions into a common hash value based on a hash function. The common access count for the plurality of regions may be indexed by the common hash value. In summary, when any one of the plurality of regions is accessed under the integrated management, the processor 110 may calculate the common hash value (i.e. access pattern) corresponding to the plurality of regions based on the address of the accessed region and may update the common access count that is indexed by the calculated common hash value.). As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claims 2, 20, and 30, taking claim 2 as exemplary, Kim teaches The method of claim 1, further comprising: comparing, after incrementing the counter, a value of the counter with a threshold value ([Kim abstract, 0045, 0080, 0083, Fig. 6] A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold. When it is determined based on the access count table 125 that a certain region of the nonvolatile memory apparatus 200 is excessively accessed, the processor 110 may perform the data inspection operation on the neighboring region of the certain region. The data inspection operation may be performed by checking the deformation degree of the data stored in the neighboring region and by selectively performing a reclaim operation for recovering the data to a state before the deformation, based on the deformation degree of the data. In step S230, the processor 110 may determine whether the updated common access count reaches a threshold. When it is determined that the updated common access count reaches the threshold (Yes), the process may proceed to step S240. When it is determined that the updated common access count does not reach the threshold (No), the process may be ended. Namely, when the updated common access count does not reach the threshold, it implies that the target region has not been excessively accessed, and thus the processor 110 may end the reliability maintenance operation.). As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claim 13, Kim teaches The method of claim 1, wherein the memory comprises a plurality of memory devices coupled with a controller of the memory ([Kim abstract, 0036-0037, Fig. 1] The data storage device 10 may include a controller 100 and a nonvolatile memory apparatus 200. The controller 100 may include a processor 110, a memory 120, and an ECC (error correction code) unit 130.). Allowable Subject Matter Claims 3-12 and 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding storage access tracking. US 20230049678 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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Prosecution Timeline

May 29, 2025
Application Filed
Sep 04, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12710890
MEMORY SYSTEMS AND METHODS OF OPERATING THEREOF, COMPUTER-READABLE STORAGE MEDIUMS
1y 11m to grant Granted Aug 18, 2026
Patent 12687977
BAD BLOCK MAPPING BASED ON BAD BLOCK DISTRIBUTION IN A MEMORY SUB-SYSTEM
2y 4m to grant Granted Jul 21, 2026
Patent 12682162
METHOD AND APPARATUS FOR SEQUENCE PROCESSING
3y 7m to grant Granted Jul 14, 2026
Patent 12650789
ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
1y 10m to grant Granted Jun 09, 2026
Patent 12650783
CONTROLLING MEMORY OVERHEAD FOR STORING INTEGRITY DATA IN SOLID STATE DRIVES
1y 8m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
86%
With Interview (-1.3%)
2y 4m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 403 resolved cases by this examiner. Grant probability derived from career allowance rate.

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