DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 05/29/2025. Claims 1-25 have been examined and are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9-10, 12, 14-15, 17-19, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev US 2017/0286286 (“Szubbocsev”).
As per independent claim 1, Szubbocsev teaches A memory system (“FIG. 1 is a schematic block diagram of a memory device 100” para 0017), comprising:
one or more memory devices (“a memory array 120.” Para 0017 and FIG. 1);
processing circuitry coupled with the one or more memory devices (“The memory device 100 includes a memory controller 110 operably coupled with a memory array 120.” Para 0017 and FIG. 1) and configured to cause the memory system to:
determine whether a first superblock comprises a first quantity of valid physical blocks below a threshold to use the first superblock as an incomplete superblock (“determine the amount of valid data for each physical block of each die managed by the first channel.” “If there are additional channels, additional blocks may be similarly searched.” Paras 0034-0035 and steps 420-430 of FIG. 4. See para 0027 for static superblocks. See FIGS. 3A-3E for example construction of dynamic superblocks);
generate a second superblock using one or more first valid physical blocks of the first superblock based at least in part on determining that the first quantity of valid physical blocks is below the threshold (“At operation 440, the dynamic superblock may be constructed including a set of physical blocks that are linked together based, at least in part, on the amount of valid data in each of the physical blocks.” Para 0036 and FIG. 4);
access the second superblock based at least in part on generating the second superblock (“After the physical blocks are erased, then the firmware can write new data to the newly available space.” Para 0038 and FIG. 4).
Szubbocsev discloses all of the claim limitations from above, but does not use a “threshold” to select the physical blocks.
However, Szubbocsev teaches “the physical block from each channel may be selected that has the least amount of valid data.” Para 0029.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “threshold”. The motivation would be that the amount of data needed to be relocated may be reduced during garbage collection in comparison to conventional methods, para 0029 of Szubbocsev.
As per dependent claim 2, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the processing circuitry is further configured to cause the memory system to: generate a pool of blocks and a cursor (“The FTL 206 may also maintain a virtual mapping of multiple physical blocks referred to herein as a ‘superblock.’” Para 0022) for the second superblock and other superblocks that include the first quantity of valid physical blocks below the threshold, wherein accessing the second superblock is based at least in part on generating the pool (“After the physical blocks are erased, then the firmware can write new data to the newly available space. The firmware may continue to read, write, and/or erase data according to the operation of the application and file system layers until the FTL determines that additional free space is needed and garbage collection is needed. A new dynamic superblock may then be constructed accordingly,” para 0038).
As per dependent claim 9, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein: the second superblock stores information as single-level cells (“memory cells of a block may be configured as single-level cells (SLC)” para 0017).
As per dependent claim 10, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the second superblock is configured to store information associated with firmware logs (“the memory controller (e.g., via firmware for the FTL) may determine that cleanup is desirable to free space in some of the physical blocks of the memory array.” Para 0033), small fragment cursors, redundant array of independent NAND (RAIN) parity, replay protected memory blocks, or any combination thereof.
As per dependent claim 12, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the processing circuitry is further configured to cause the memory system to: generate a third superblock using one or more second valid physical blocks of the first superblock, wherein a second quantity of the valid physical blocks in the second superblock is different than a third quantity of the valid physical blocks in the third superblock (See FIGS. 3A-3E).
As per dependent claim 14, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the processing circuitry is further configured to cause the memory system to: scan a plurality of superblocks of a memory device to identify valid physical blocks and invalid physical blocks, wherein determining that the first superblock comprises the first quantity of valid physical blocks is based at least in part on scanning the plurality of superblocks (“In the example shown in FIG. 3B, the FTL 206 may search the dies 301, 302 of the first channel and select block 2 of the first die 301 because (6) is the lowest valid data for physical blocks across the first channel.” Para 0029).
As per dependent claim 15, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the processing circuitry is further configured to cause the memory system to: receive an access command based at least in part on generating the second superblock, wherein accessing the second superblock is based at least in part on receiving the access command (“The memory controller 110 may be configured to control operation of the memory array 120, including issuing the commands for reading, writing, and/or erasing.” Para 0019).
As per dependent claim 17, Szubbocsev discloses the system of claim 1. Szubbocsev teaches wherein the second superblock comprises a second quantity of valid physical blocks that is less than a third quantity of valid physical blocks of a complete superblock and less than a fourth quantity of valid physical blocks of the incomplete superblock (See FIGS. 3A-3E).
As per claims 18-19, these claims are rejected based on arguments provided above for similar rejected claims 1-2. For computer program product on a non-transitory computer readable medium, see FIG. 5 of Szubbocsev where memory device 520 may store computer executable instructions for execution by the processor 510.
As per claims 23-24, these claims are rejected based on arguments provided above for similar rejected claims 1-2.
Claims 3, 16, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev in view of Gonzalez et al. US 2005/0144516 (“Gonzalez”).
As per dependent claim 3, Szubbocsev discloses the system of claim 2. Szubbocsev teaches and superblocks that include the first quantity of valid physical blocks below the threshold (See FIGS. 3A-3E).
Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Gonzalez teaches wherein the pool of blocks includes incomplete superblocks (“When a physical block within a metablock fails, the metablock can no longer be used as is. One simple solution would be to map that metablock out of the address space and never use it again. This is the only solution available if the system only has one single bad physical block and no spare blocks are available.” Para 0050 and FIG. 6).
Given the teaching of Gonzalez, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the pool of blocks includes incomplete superblocks”. The motivation would be that good blocks associated with a failed metablock can be used to create other metablocks, para 0050 of Gonzalez, improving space availability.
As per dependent claim 16, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Gonzalez teaches wherein the first superblock comprises the incomplete superblock based at least in part on determining that the first quantity of valid physical blocks is below the threshold (“When a physical block within a metablock fails, the metablock can no longer be used as is. One simple solution would be to map that metablock out of the address space and never use it again. This is the only solution available if the system only has one single bad physical block and no spare blocks are available.” Para 0050 and FIG. 6).
Given the teaching of Gonzalez, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the first superblock comprises the incomplete superblock based at least in part on determining that the first quantity of valid physical blocks is below the threshold”. The motivation would be that good blocks associated with a failed metablock can be used to create other metablocks, para 0050 of Gonzalez, improving space availability.
As per dependent claims 20 and 25, these claims are rejected based on arguments provided above for similar rejected claim 3.
Claims 4-5 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev in view of Post et al. US 2012/0047409 (“Post”).
As per dependent claim 4, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Post teaches wherein the processing circuitry is further configured to cause the memory system to: update a bad block table to indicate the one or more first valid physical blocks assigned to the second superblock after generating the second superblock, wherein accessing the second superblock is based at least in part on updating the bad block table (“Once the dynamic super block has been formed, the NVM interface can use any suitable approach to communicate the existence of the super block to a translation layer (e.g., translation layer 214 of FIG. 2). For example, the NVM interface can set a flag indicating that a dynamic super block is available for programming.” Para 0070).
Given the teaching of Post, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the processing circuitry is further configured to cause the memory system to: update a bad block table to indicate the one or more first valid physical blocks assigned to the second superblock after generating the second superblock, wherein accessing the second superblock is based at least in part on updating the bad block table”. The motivation would be that the dynamic superblock can be more reliable, para 0071 of Post.
As per dependent claim 5, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Post teaches wherein the processing circuitry is further configured to cause the memory system to: update a mapping that indicates physical blocks assigned to superblocks that include the first quantity of valid physical blocks below the threshold after generating the second superblock, wherein accessing the second superblock is based at least in part on updating the mapping (“Once the dynamic super block has been formed, the NVM interface can use any suitable approach to communicate the existence of the super block to a translation layer (e.g., translation layer 214 of FIG. 2). For example, the NVM interface can set a flag indicating that a dynamic super block is available for programming.” Para 0070).
Given the teaching of Post, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the processing circuitry is further configured to cause the memory system to: update a mapping that indicates physical blocks assigned to superblocks that include the first quantity of valid physical blocks below the threshold after generating the second superblock, wherein accessing the second superblock is based at least in part on updating the mapping”. The motivation would be that the dynamic superblock can be more reliable, para 0071 of Post.
As per dependent claims 21-22, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 4-5.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev in view of Byun US 2021/0117089 (“Byun”).
As per dependent claim 6, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Byun teaches wherein the processing circuitry is further configured to cause the memory system to: assign a first physical block of the second superblock to a complete superblock; assign a second physical block of the complete superblock to the second superblock; and access the second superblock after assigning the second physical block to the second superblock (“Referring to FIGS. 1 and 5B, it may be seen that the controller 130 swaps the source block BLOCK<20>, included in the first mixed super block SB0, for the general block BLOCK<2100> included in the fourth mixed super block SB3.” Para 0129).
Given the teaching of Byun, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the processing circuitry is further configured to cause the memory system to: assign a first physical block of the second superblock to a complete superblock; assign a second physical block of the complete superblock to the second superblock; and access the second superblock after assigning the second physical block to the second superblock”. The motivation would be that the invention classifies super blocks into different groups that enhance background operations such as garbage collection operation, para 0016 of Byun.
As per dependent claim 7, Szubbocsev in combination with Byun discloses the system of claim 6. Szubbocsev may not explicitly disclose, but Byun teaches wherein the processing circuitry is further configured to cause the memory system to: update a bad block table to indicate that the first physical block is assigned to the complete superblock and to indicate that the second physical block is assigned to the second superblock, wherein accessing the second superblock is based at least in part on updating the bad block table (“the background operation performed on the memory device 150 may include an operation of storing map data stored in the controller 130 in the memory blocks BLOCK<0, 1, 2, . . . > of the memory device 150,” para 0083).
The same motivation that was utilized for combining Szubbocsev and Byun as set forth in claim 6 is equally applicable to claim 7.
As per dependent claim 8, Szubbocsev in combination with Byun discloses the system of claim 6. Szubbocsev may not explicitly disclose, but Byun teaches wherein the processing circuitry is further configured to cause the memory system to: update a mapping to indicate that the first physical block is assigned to the complete superblock and to indicate that the second physical block is assigned to the second superblock, wherein the mapping indicates physical blocks assigned to superblocks that include the first quantity of valid physical blocks below the threshold, wherein accessing the second superblock is based at least in part on updating the mapping (“the background operation performed on the memory device 150 may include an operation of storing map data stored in the controller 130 in the memory blocks BLOCK<0, 1, 2, . . . > of the memory device 150,” para 0083).
The same motivation that was utilized for combining Szubbocsev and Byun as set forth in claim 6 is equally applicable to claim 7.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev in view of Huang et al. US 2020/0042201 (“Huang”).
As per dependent claim11, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Huang teaches wherein the second superblock is part of a replay protected memory block (RPMB) region of the memory system (“Group_C can include a specialized data class including RPMB or boot data. Here, superblocks can be allocated to user data, OP, SLC cache L2P data, and firmware data while partial superblocks are used to store RPMB or boot data blocks.” Para 0053).
Given the teaching of Byun, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein the second superblock is part of a replay protected memory block (RPMB) region of the memory system”. The motivation would be that RPMB requirements are low and are readily satisfied by three-plane superblocks, para 0053 of Huang.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Szubbocsev in view of Qiu et al. US 2024/0192877 (“Qiu”).
As per dependent claim13, Szubbocsev discloses the system of claim 1. Szubbocsev may not explicitly disclose, but in an analogous art in the same field of endeavor, Qiu teaches wherein one of the second superblock or the third superblock comprises a single physical block (“The super block includes at least one physical block.” Para 0011).
Given the teaching of Qiu, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Szubbocsev with “wherein one of the second superblock or the third superblock comprises a single physical block”. The motivation would be that the invention increases quantity of superblocks in the redundant space (OP) which improves the overall performance, para 0010 of Qiu.
Conclusion
Another close prior art reference Liu US 2019/0179741 (“Liu”) was considered by the Examiner. Liu suggests against the patentability of the instant claimed invention. For example, see paragraphs [0005] and [0124] of Liu.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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