Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 19/223,000, the amendment filed on 8/12/2026 is herein acknowledged. Claims 1, 3-5, 7-11, 13, 15-20 have been amended. Claim 12 has been canceled and claim 21 has been added. Claims 1-11 and 13-21 are pending.
In response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the examiner.
OBJECTIONS
Claim Objections
Claim 1 is objected to because of the following informalities: The limitation “wordline” in line 6 appears to be a typographical error and should be amended to read “word line”. Appropriate correction is required.
As per claim 9, the limitations “wherein the first page of the block of memory is determined based on a first utilized amount of the memory,” appears to inadvertently omit that the first utilized among refer to a first utilized amount of the block of memory. Thus, these limitations should be corrected to read “wherein the first page of the block of memory is determined based on a first utilized amount of the block of memory,”. Appropriate correction is required.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As per claim 21, Applicant’s Specification does not provide support for locking based on “an occupied amount of the memory” as recited in newly added claim 21.
While the Specification discusses locking portions of memory and unlocking pages groups upon other groups being filled, see relevant portions of the Specification below:
[0051] To control the sequence in which pages in the unoccupied portion of memory 404 are filled with data, some pages and/or page groups 415 may be activated (e.g., to enable data to be stored in them), while other pages and/or page groups 415 may be locked (e.g., to prevent data from being stored in them). For example, as illustrated in FIG. 4A, page groups 415-M and/or 415-1 may be activated such that frequently accessed data may be stored in one or more pages in page group 415-M, and infrequently accessed data may be stored in one or more pages in page group 415-1, whereas page groups 415-M-1 through 415-2 may be locked (e.g., not available to store data).
[0053] For example, referring to FIG. 4B, page group 415-M may be effectively filled (e.g., unable to receive additional write data), and thus, page group 415-M-1 (e.g., the next strongest wordlines) may be activated to receive additional write data (e.g., relatively frequently accessed data). Additionally, or alternatively, page group 415-1 may be effectively filled (e.g., unable to receive additional write data), and thus, page group 415-2 (e.g., the next weakest wordlines) may be activated to receive additional write data (e.g., relatively infrequently accessed data), Page groups 415-M-2 through 415-3 may remain locked, for example, until one or both of page groups 415-M-1 and/or 415-2 are filled.
[0059] At the first utilization level illustrated in FIG. 5A, a portion 509 of memory 504 may be utilized (e.g., occupied with stored data). Some or all of the unoccupied portion of memory 504 may be arranged in page groups 515-M through 515-1 of pages having the same or similar endurance indicated by an endurance index. Page group 515-M may be active to receive new write data, and page groups 515-M-1 through 515-1 may be locked. New data to be written to memory 504 may be written to one or more pages in page group 515-M regardless of an access characteristic (e.g., frequency of use) of the data.
(figs. 5A and 5B)
Applicant’s Specification does not discuss the locking a portion of memory also based on an occupied amount of the memory since while locking occurs to portions of memory to prevent data from being stored, it does not take into consideration the occupied amount of memory to perform the locking. Appropriate correction/clarification is required.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0159619) in view of GOPALAKRISHNAN et al. (US 20230359378).
1. A device comprising: a memory comprising: [Oh teaches memory device 200 (fig. 1 and related text)]
a first page within a block of the memory, the first page accessible by a first word line and having a first endurance characteristic; and [Oh teaches “[0033] As an example, with respect to a first cell block included in the memory cell array 210, the first cell block may include a plurality of pages and the endurance determination circuit 130 may perform a counting operation for determining endurance in units of pages. For example, when determining endurance of a first page included in the first cell block, the write counter 131 may count the number of writing operations on the first cell block and output a counted value and may count the number of writing operations on the first page and output a counted value.” Where data 1 to data K of page 1 is accessible by WL1 (fig. 5 and related text)]
a second page within the block of the memory, the second page accessible by a second wordline and having and having a second endurance characteristic different from the first endurance characteristic; [Oh teaches “[0033] As an example, with respect to a first cell block included in the memory cell array 210, the first cell block may include a plurality of pages and the endurance determination circuit 130 may perform a counting operation for determining endurance in units of pages. For example, when determining endurance of a first page included in the first cell block, the write counter 131 may count the number of writing operations on the first cell block and output a counted value and may count the number of writing operations on the first page and output a counted value.” Where pages are accessible by the different word lines WL1 to WL N (fig. 5 and related text)]
and a device controller [Oh teaches memory controller 100 (fig. 1 and related text)]
configured to perform an operation comprising storing, in a page of the memory, data [Oh teaches write request S22 (fig. 9A and related text; par. 0080) write request S31 to write a data page (fig. 9B and related text; par. 082)];
wherein the storing the data is based on: an access characteristic of the data; and the first endurance characteristic of the first page of the block of memory [Oh teaches “[0083]… For example, when the write requests with respect to a plurality of pages included in the cell block are received, the write counting value of the cell block may increase, and when the write counting value of the cell block reaches the reference value Nref, it may be determined whether the endurance of the page in the cell block has degraded.” “[0084]… when it is determined that the endurance of the page has degraded, the wear-leveling process may be performed or criterion for performing the wear-leveling process may be changed (S35).” “[0037]… the data of the first page having degraded endurance may be copied to another page based on the wear-leveling process performed in units of pages... In example embodiments, the data of the first page may be copied to another page in the first cell block...” note if the write count value does not exceed Nref, writes continue to be processed]; thus, storing data to a block at least based on the first endurance characteristic of the first page of the block of memory, but Oh does not expressly refer to storing the data also based on an access characteristic of the data; however, regarding these limitations, GOPALAKRISHNAN teaches [“[0030] By segregating the data thusly, frequently read data (e.g., hot data) may be read faster than cold data because it is stored in pages with a reduced number of senses. This may improve the rate at which hot data is read and may therefore improve performance of the storage device. Moreover, by segregating the hot data to low sense pages, the MLC read endurance may be increased. For example, stress on the MLC may be reduced by storing hot data in low-sense pages because instead of storing the hot data on a page that requires three senses, it is stored on a page that only requires one.” “[0058] During relocation from the SLC block to the TLC block, the data contained in all three SLC blocks may be copied to a respective page in the TLC block. As illustrated, the first cold data 702, the second cold data 704, and the hot data 706 are folded into one TLC block 708 (e.g., BICS5-X3, wherein the encoding is 1-3-3). Because the hot data 706 is associated with the block with the highest read command count, the hot data 706 may be folded as lower page (e.g., LP-1) in the TLC block 708 so that only one sense is required to read the hot data from the TLC block 708. The first cold data 702 and the second cold data 704 may be copied to the middle page (e.g., MP-3) and the upper page (e.g., UP-3). Accordingly, the hottest data (e.g., the data this is associated with the most read commands) only requires one sense, while relatively colder data may require more senses. By this, the data stored in the TLC block 708 may be read with fewer senses than if the hot data required three senses.” Where pages requiring more senses correspond to lower endurance pages than pages requiring less sense operations in the TLC block (see figs. 5 and 7a, 7b and related text))].
Oh and GOPALAKRISHNAN are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Oh to include access characteristics when deciding in which page of a block to store data, as taught GOPALAKRISHNAN since doing so would provide the benefits of [“[0030] By segregating the data thusly, frequently read data (e.g., hot data) may be read faster than cold data because it is stored in pages with a reduced number of senses. This may improve the rate at which hot data is read and may therefore improve performance of the storage device. “ as well as reduced bottlenecking (par. 0031)].
Therefore, it would have been obvious to combine Oh and GOPALAKRISHNAN for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The device of claim 1, wherein: the access characteristic comprises an access frequency; and [GOPALAKRISHNAN teaches hot data (par. 0030) hot, warm and cold data (par. 0063)] the endurance characteristic comprises a number of program cycles [Oh teaches “[0035] The determination logic 133 may determine whether the endurance of the first page has degraded, based on the counting results of the write counter 131 and the cell counter 132.”].
3. The device of claim 1, wherein the data comprises first data, the access characteristic is a first access characteristic, and the device controller is configured to perform one or more operations comprising: storing, in the second page of the block of memory, second data; wherein the storing the second data is based on: a second access characteristic of the second data; and the second endurance characteristic of the second page of the block of memory [The rationale in the rejection of claim 1 is herein incorporated. According to Oh, pages may have different endurance values (pars. 0037, 0083-0084), where warm and cold pages are also stored (see par. 0063 of GOPALAKRISHNAN)].
4. The device of claim 1, wherein the device controller is configured to determine the first endurance characteristic of the first page of the block of memory based on at least one of an indication or a structure of the block of memory [Oh teaches “[0031] According to the embodiment, the endurance determination circuit 130 may predict or determine whether the endurance degrades as the lifespan of the memory device 200 is running out (or as writing, erasing and/or reading cycles increase). For example, the endurance determination circuit 130 may determine the endurance based on various units of the memory cell array 210, and as an example, the endurance determination circuit 130 may determine the endurance in units of pages, word lines, cell blocks, etc. of the memory cell array 210. According to the embodiment, the endurance determination circuit 130 may determine the endurance of the memory device 200 by using various methods; for example, the endurance determination circuit 130 may determine whether the endurance of the memory device 200 has degraded according to various kinds of counting results and various kinds of criteria. Hereinafter, an example in which the endurance determination circuit 130 determines the endurance in units of pages will be described below, but the endurance may be determined in other various units.” “[0036] The determination logic 133 may determine whether the endurance of the first page degrades based on various determination criteria. For example, the above four counting results may be variously combined to include at least two counting results, and the degradation in the endurance may be determined according to the above combinations. As an example, whether the endurance of the first page degrades may be determined by determining the number of error cells or the number of off-cells in the data read from the first page, together with the number of writing operations on the first cell block. As another example, whether the endurance of the first page degrades may be determined by determining the number of error cells or the number of off-cells in the data read from the first page, together with the number of writing operations on the first page.” “[0043] In the above embodiments, it is described that whether the endurance of the page has degraded is determined, but terms may be variously defined. As an example, according to the determination of the embodiments, a result indicating that endurance failure occurs in the page may be output.”. GOPALAKRISHNAN teaches lower, middle and upper pages requiring different number of sense operations for data reads which cause different stress levels on the memory (pars. 0030, 0063)].
5. The device of claim 1, wherein the device controller is configured to determine the first endurance characteristic of the first page of the block of memory based on monitoring the first page of the block of memory [The rationale in the rejection of claim 4 is herein incorporated where endurance determination circuit 130 includes determination logic 133 which monitors endurance at the page level (see fig. 1 and related text; pars. 0046, 0049, 0070)].
6. The device of claim 1, wherein the device controller is configured to determine the access characteristic of the data based on monitoring one or more accesses of the data [Oh teaches “[0074] Referring to FIGS. 6 and 7, the memory controller may read data from the first page of the memory device in response to a read command from the host, may identify a write counting value of a block unit for determining the endurance (S11), and may identify a write counting value of a page unit (or word line unit) (S12). In addition, it may be determined whether the endurance of the first page degrades as described above (S13), and a wear-leveling process for ensuring reliability of the data read from the first page may be performed (S14).”].
7. The device of claim 1, wherein the device controller is configured to: receive an indication; and determine the endurance characteristic of the first page of the block of memory based on the indication [Oh teaches “[0043] In the above embodiments, it is described that whether the endurance of the page has degraded is determined, but terms may be variously defined. As an example, according to the determination of the embodiments, a result indicating that endurance failure occurs in the page may be output… [0046] Referring to FIGS. 1 and 2, the endurance determination circuit 130 includes the write counter 131 and the cell counter 132, and the write counter 131 may include a block unit counter 131_1 and a page unit counter 131_2. The cell counter 132 may include an error cell counter 132_1 and an off-cell counter 132_2 (or, on-cell counter). Also, the endurance determination circuit 130 may further include the determination logic 133. The determination logic 133 may receive first counting information Info_CNT1 from the write counter 131 and second counting information Info_CNT2 from the cell counter 132 and may output determination information Det_endur indicating a result of determining the endurance obtained by processing the received information… [0070] It may be determined whether the endurance of the first page degrades based on the identified counting values (S13). As an example, the counting values may be respectively compared with corresponding predetermined reference values, and it may be determined whether the endurance of the first page degrades according to a comparison result. Each of the counting values may indicate an endurance degradation level of the first page, and it may be determined whether the endurance degradation level exceeds a predetermined reference. As an example, when the counting value of a cell block unit and the counting value of the page unit are both greater than respectively corresponding reference values, it may be finally determined that the endurance of the first page has degraded.
15. A method comprising: storing, in a page of a block of memory, data; wherein the first page has a first endurance characteristic and is accessible by a first word line; the block of memory comprises a second page accessible by a second word line and having a second endurance characteristic; wherein the storing the data is based on: an access characteristic of the data; and the first endurance characteristic of the first page of the block of memory [The rationale in the rejection of claim 1 is herein incorporated].
16. The method of claim 15, wherein the data comprises first data, the access characteristic is a first access characteristic, the method further comprising: storing, in the second page of the block of memory, second data; wherein the storing the second data is based on: a second access characteristic of the second data; and the second endurance characteristic of the second page of the block of memory [The rationale in the rejection of claim 3 is herein incorporated].
17. The method of claim 15, wherein the first endurance characteristic of the first page of the block of memory is based on at least one of a structure of the block of memory, an indication, or monitoring the first page of the block of memory [The rationale in the rejection of claims 4-5 is herein incorporated].
18. The method of claim 15, wherein the first access characteristic of the data is based on one or more of an indication or monitoring one or more accesses of the data [The rationale in the rejection of claim 6 is herein incorporated].
Claims 8-9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0159619) in view of GOPALAKRISHNAN et al. (US 20230359378) as applied in the rejection of claim 1 above, and further in view of Gorobets et al. (US 20150143030).
8. The combination of Oh and GOPALAKRISHNAN teaches The device of claim 1, but does not expressly disclose wherein the storing the data is further based on a utilized amount of the block of memory; however, regarding these limitations Gorobets teaches [“[0080]… MLC blocks that are likely to be reclaimed before they are full may be programmed using a programming scheme that programs lower pages of all word lines first and only programs upper pages after all lower pages are programmed.” “[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).” “[0083]… in a memory that stores one or more middle pages (e.g. an 8-state, 3-bit per cell memory, that stores a lower, middle, and upper page in each physical page), the lower pages may be programmed first. Then, the one or more middle pages may be programmed after all lower pages are programmed. If there are multiple middle pages (e.g. 4-bits per cell, 4 logical pages per physical page) the middle pages may be filled after the lower pages (i.e. lower middle page filled first, then upper middle page). Only after middle pages are filled are the upper pages programmed. In general, the higher level pages take more time to program. Programming logical pages in order from fastest to slowest ensures that fast capacity is more heavily used and slow capacity is less heavily used because blocks are frequently reclaimed before they are completely filled.”], where storing to all lower level pages are done first until they are all full or based on the utilized amount of the block of memory, then the system/method begins programming upper level pages of the block to use the upper level page capacity.
Oh, GOPALAKRISHNAN and Gorobets are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of OH and GOPALAKRISHNAN to have the storing the data is further based on a utilized amount of the block of memory in the manner taught by Gorobets, where lower level pages are filled before filling upper level pages in the memory since doing so would provide the benefits of [“[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).”].
Therefore, it would have been obvious to combine Oh, GOPALAKRISHNAN and Gorobets for the benefit of creating a storage system/method to obtain the invention as specified in claim 8.
9. Gholamipour teaches The device of claim 1, wherein the data comprises first data, and the device controller is further configured to perform one or more operations comprising: storing, in the second page of the block of memory, second data [The rationale in the rejection of claim 1 is herein incorporated. According to Oh, pages may have different endurance values (pars. 0037, 0083-0084), where warm and cold pages are also stored (see par. 0063 of GOPALAKRISHNAN)]; but does not expressly disclose wherein the first page of the block of memory is determined based on a first utilized amount of the memory, and the second page of the block of memory is determined based on a second utilized amount of the block of memory; however, regarding these limitations, Gorobets teaches [“[0080]… MLC blocks that are likely to be reclaimed before they are full may be programmed using a programming scheme that programs lower pages of all word lines first and only programs upper pages after all lower pages are programmed.” “[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).” “[0083]… in a memory that stores one or more middle pages (e.g. an 8-state, 3-bit per cell memory, that stores a lower, middle, and upper page in each physical page), the lower pages may be programmed first. Then, the one or more middle pages may be programmed after all lower pages are programmed. If there are multiple middle pages (e.g. 4-bits per cell, 4 logical pages per physical page) the middle pages may be filled after the lower pages (i.e. lower middle page filled first, then upper middle page). Only after middle pages are filled are the upper pages programmed. In general, the higher level pages take more time to program. Programming logical pages in order from fastest to slowest ensures that fast capacity is more heavily used and slow capacity is less heavily used because blocks are frequently reclaimed before they are completely filled.”], where storing to all lower level pages are done first until they are all full or based on the utilized amount of the block of memory, then the system/method begins programming upper level pages of the block to use the upper level page capacity.
Oh, GOPALAKRISHNAN and Gorobets are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of OH and GOPALAKRISHNAN to include wherein the first page of the block of memory is determined based on a first utilized amount of the memory, and the second page of the block of memory is determined based on a second utilized amount of the block of memory as taught by Gorobets, where lower level pages are filled before filling upper level pages in the memory since doing so would provide the benefits of [“[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).”].
Therefore, it would have been obvious to combine Oh, GOPALAKRISHNAN and Gorobets for the benefit of creating a storage system/method to obtain the invention as specified in claim 9.
19. The method of claim 15, wherein the storing the data is further based on a utilized amount of the block of memory [The rationale in the rejection of claim 8 is herein incorporated].
20. The method of claim 15, wherein the data comprises first data, the method further comprising: storing, in a second page of the block of memory, second data; wherein the first page of the memory is based on a first utilized amount of the memory, and the second page of the memory is based on a second utilized amount of the block of memory [The rationale in the rejection of claim 9 is herein incorporated].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0159619) in view of GOPALAKRISHNAN et al. (US 20230359378)) as applied in the rejection of claim 1 above, and further in view of Palmer et al. (US 2021/0200631).
10. The device of claim 1, wherein the device controller is configured to perform, based on the storing the data, a garbage collection operation on the first page of the block of memory [GOPALAKRISHNAN teaches “[0054] As discussed, hot data may be stored in pages with relatively low senses. For example, when valid hot data is copied from an SLC/MLC block and moved to another MLC (e.g., BICS5-X4) during a garbage collection (GC) operation, the hot data may be moved to the lower page (LP-1) or middle page (MP-2). Whether data can be considered hot/cold depends on whether the SLC/MLC block from which the data is copied has a high number of reads relative to other SLC/MLC blocks, or the number of reads associate with the SLC/MLC block exceeds a threshold value.”where as garbage collection is performed, it covers it being performed on pages of the memory]; but the combination does not expressly refer to garbage collection operation on the page of the memory; however, regarding these limitations, Palmer teaches [“The device then accesses the stale data to perform GC on a page level instead of managing whole blocks, thereby reducing WA and increasing SSD endurance.” (par. 0031)].
Oh, GOPALAKRISHNAN and Palmer are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Oh and GOPALAKRISHNAN to include garbage collection operation on the page of the memory as taught by Palmer, since doing so would provide the benefits of [“reducing WA and increasing SSD endurance.” (par. 0031)].
Therefore, it would have been obvious to combine Oh, GOPALAKRISHNAN and Palmer for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
Claims 11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Gholamipour et al. (US 20190108889) in view of Gorobets et al. (US 20150143030).
11. A device comprising: a memory comprising a first page having a first endurance characteristic and a second page having a second endurance characteristic different from the first endurance characteristic; and [Gholamipour teaches “Those goals may be to match expected media endurance capabilities against host workloads of concern. A specific example is to choose group size and gap movements that would disrupt a series of sequential writes to an individual logical address before reaching an endurance limit of a physical page, e.g. for expected endurance of about 5E5 writes “ (par. 0104) “[0116] FIG. 16 shows an example of a memory in which non-volatile memory cells are mapped into 5 regions that are classified according to their expected endurance. Regions 1 and 5 are classified as low endurance regions. Region 2 is classified as a high endurance region. Regions 3 and 4 are classified as medium endurance regions. Each region may be formed of physical areas that are expected to have similar endurance characteristics (similar expected endurance limits) and may be physically dispersed across multiple devices. Mapping of non-volatile memory cells into regions may be performed in any suitable sized unit (e.g. by page, block, or other unit) and may be a static mapping or may be dynamic, i.e. some remapping may occur during operation. Mapping of a set of non-volatile memory cells into a plurality of regions may be performed by a memory controller (e.g. according to firmware) and may be performed as part of an initialization and/or subsequent to initialization.” Where pages in each of the regions have different endurance characteristics]
a device controller configured to perform one or more operations comprising: [Gholamipour teaches “Controller 122 is included in the same memory device, such as memory device 100 (e.g., a removable storage card) as the one or more memory die 108. However, in other systems, the Controller can be separated from the memory die 108. “ (par. 0047)]
storing first data in the first page of the memory based on a first occupied amount of memory, first access characteristic of the first data, and the first endurance characteristic; and storing second data in the second page of the memory based on a second occupied amount of the memory, a second access characteristic of the second data, and the second endurance characteristic [Gholamipour teaches “[0118] FIGS. 17A-B illustrate a mapping of logical pages of FIG. 15 to regions of FIG. 16 according to access frequency and endurance. Logical pages A-D, which have low expected access frequency, are mapped to region 1, which has low endurance. Logical pages M-P, which have high expected access frequency, are mapped to region 2, which has high endurance. Logical pages E-H and I-L, which have medium expected access frequency are mapped to region 4, which has medium endurance. A gap for an inter-region wear leveling scheme is assigned to region 5, which has low endurance. This may represent an initial mapping in a memory so that at least initially data is assigned in a manner that accounts for different expected access patterns and different endurance characteristics.”] but does not expressly disclose the storing first page of the memory based on a first occupied amount of memory, … the storing in the second page based on a second utilized amount of the memory… storing second data in the second page of the memory based on a second occupied amount of the memory; however, regarding these limitations, Gorobets teaches [“[0080]… MLC blocks that are likely to be reclaimed before they are full may be programmed using a programming scheme that programs lower pages of all word lines first and only programs upper pages after all lower pages are programmed.” “[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).” “[0083]… in a memory that stores one or more middle pages (e.g. an 8-state, 3-bit per cell memory, that stores a lower, middle, and upper page in each physical page), the lower pages may be programmed first. Then, the one or more middle pages may be programmed after all lower pages are programmed. If there are multiple middle pages (e.g. 4-bits per cell, 4 logical pages per physical page) the middle pages may be filled after the lower pages (i.e. lower middle page filled first, then upper middle page). Only after middle pages are filled are the upper pages programmed. In general, the higher level pages take more time to program. Programming logical pages in order from fastest to slowest ensures that fast capacity is more heavily used and slow capacity is less heavily used because blocks are frequently reclaimed before they are completely filled.”], where storing to all lower level pages are done first until they are all full or based on the utilized amount of the memory, then the system/method begins programming upper level pages of the block to use the upper level page capacity.
Gholamipour and Gorobets are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Gholamipour to have the storing in the second page based on a second utilized amount of the memory… storing second data in the second page of the memory based on a second occupied amount of the memory as taught by Gorobets, where lower level pages are filled before filling upper level pages in the memory since doing so would provide the benefits of [“[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).”].
Therefore, it would have been obvious to combine Gholamipour and Gorobets for the benefit of creating a storage system/method to obtain the invention as specified in claim 11.
13. The device of claim 11, wherein the device controller is further configured to perform one or more operations comprising: operating, based on the first occupied amount of the memory, a first group of pages of the memory comprising the first page of the memory; and operating, based on the second occupied amount of the memory, a second group of pages of the memory comprising the second page of the memory [[“[0080]… MLC blocks that are likely to be reclaimed before they are full may be programmed using a programming scheme that programs lower pages of all word lines first and only programs upper pages after all lower pages are programmed.” “[0082]… By using faster, lower page capacity first, and only using slower, upper page capacity later, overall speed is increased because overall use shifts to faster, lower pages, and shifts away from slower, upper pages. Reading may also be faster because the number of blocks that contain only lower page data when they are consolidated increases. Data can be more rapidly copied from such blocks because only lower page reading is required (no upper page read).” “[0083]… in a memory that stores one or more middle pages (e.g. an 8-state, 3-bit per cell memory, that stores a lower, middle, and upper page in each physical page), the lower pages may be programmed first. Then, the one or more middle pages may be programmed after all lower pages are programmed. If there are multiple middle pages (e.g. 4-bits per cell, 4 logical pages per physical page) the middle pages may be filled after the lower pages (i.e. lower middle page filled first, then upper middle page). Only after middle pages are filled are the upper pages programmed. In general, the higher level pages take more time to program. Programming logical pages in order from fastest to slowest ensures that fast capacity is more heavily used and slow capacity is less heavily used because blocks are frequently reclaimed before they are completely filled.”], where storing to all lower level pages are done first until they are all full or based on the utilized amount of the block of memory, then the system/method begins programming upper level pages of the block to use the upper level page capacity.
14. The device of claim 13, wherein the first group of pages is based on one or more of a structure of the memory or an indication stored in the memory [Ghloamipour teaches “ For example, certain areas may have different media properties such as low expected endurance because of physical characteristics of memory cells while other areas may have high expected endurance, e.g. memory cells at different physical levels above a substrate in a 3-D memory array may have different media properties including endurance characteristics.” (par. 0043) “[0115] In some memory arrays, some areas of the memory may have less desirable media properties than others. For example, in memories some layers may have lower endurance, retention, voltage disturbs, bit error rate accumulations, or media predictability than others. In one example, locations with lower or higher endurance may be known for a given memory design and may be common to all memories of a given design so that a prediction of endurance may be made prior to use. Endurance predictions may also be obtained from testing, or observed behavior (e.g. error rate found by ECC), and indications of endurance expectations may be recorded during testing for later use. Physical areas with similar media property expectations may be assigned to the same region so that memory cells within a given region have similar endurance expectations…”. Gorobets teaches MLC blocks having lower level and upper level pages and TLC blocks having lower, middle and upper level pages (see pars. 0080-0083)].
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Gholamipour et al. (US 20190108889) in view of Gorobets et al. (US 20150143030) as applied in the rejection of claim 11 above, and further in view of Yang (US 20160314847).
21. The combination of Gholamipour and Gorobets teaches The device of claim 11, wherein the device controller is further configured to perform one or more operations comprising locking a portion of the memory based on one or more endurance characteristics of the portion of the memory and an occupied amount of the memory [Gorobets teaches “[0096]… These blocks may be operated using a lower page first scheme in which lower page programming precedes upper page programming significantly. In some cases, all lower page programming in such a block occurs before any upper page programming.” Thus, at least initially, upper pages are made unavailable for programming, until the lower pages are programmed or occupied but making these pages unavailable in Gorobets is not referred to as locking] and the combination of Gholamipur and Gorobets does not expressly disclose locking a portion of the memory based on one or more endurance characteristics of the portion of the memory; however, regarding these limitations, Yang teaches [“[0082]… In the example of FIG. 13, a weak block that experiences a high number of erratic bits is locked out (made unavailable) sooner in a given cycle than a block that experiences a smaller number of erratic bits. Thus, in FIG. 13, the weakest block experiences fewer cycles in a given phase. For example, the weakest block starts the second phase with a real PEC that is less than the strongest block by Dpec. It can be seen that this system reduces wear on weaker blocks (blocks with higher numbers of erratic bits) and increases wear on stronger blocks (blocks with lower numbers of erratic bits). Thus, the system achieves wear concentration in blocks that are better suited to high wear and achieves wear reduction in blocks that are less suited to high wear. Such uneven wear distribution is tailored to block-specific characteristics and is thus highly adaptive.” (fig. 13 and related text) Where “[0083]… If the EBC exceeds the threshold then the block is made unavailable for use 417 for the remainder of the current operating phase (i.e. for as long as the current parameters remain in use). A determination is made as to how many blocks are unavailable 419. If the number or percentage of unavailable blocks does not exceed a limit then the memory continues to operate other blocks with the current parameters 421. However, if the number or percentage of unavailable blocks exceeds the limit then a trim operation is performed 423 so that a new set of block access parameters are implemented for all blocks and blocks that were made unavailable during the prior phase are made available again.” (fig. 14 and related text) thus teaching locking blocks based on endurance characteristics, where, based], where Yang teaches blocks are locked in order to make them unavailable.
Gholamipour, Gorobets and Yang are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Gholamipour and Gorobets to include locking a portion of the memory based on one or more endurance characteristics of the portion of the memory as taught by Yang, and refer to the making of the unavailable pages of Gorobets until lower level pages are full as locking these pages, as taught by Yang since doing so would provide the benefits of [“[0082]… It can be seen that this system reduces wear on weaker blocks (blocks with higher numbers of erratic bits) and increases wear on stronger blocks (blocks with lower numbers of erratic bits). Thus, the system achieves wear concentration in blocks that are better suited to high wear and achieves wear reduction in blocks that are less suited to high wear. Such uneven wear distribution is tailored to block-specific characteristics and is thus highly adaptive.” ].
Therefore, it would have been obvious to combine Gholamipour and Gorobets with Yang for the benefit of creating a storage system/method to obtain the invention as specified in claim 21.
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 8/12/2026 with respect to the prior art rejections have been fully considered but they are moot in view of new grounds of rejection.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Lin US 20110280074 teaches “[0024] Before the controller 212 writes target data to the flash memory 214, the controller 212 determines whether the target data is important data. If the target data is ordinary data rather than important data, the controller 212 writes the target data to the flash memory 204 according an ordinary procedure. For example, if the controller 212 wants to write ordinary data to the block 221, the controller 212 directs the flash memory 214 to sequentially write to the pages 221a.about.221n of the block 221 without determining whether the pages 221a.about.221n are strong pages, weak pages, or very weak pages. On the other hand, when the target data is important data, the controller 212 merely uses strong pages of a block to store the target data, and write predetermined data to the weak pages and the very weak pages corresponding to the strong pages, wherein the predetermined data, stored in the weak pages and the very weak pages, extends the data duration of the target data stored in the corresponding strong pages. Thus, when the important data is read from the flash memory 214 with a high frequency, the read-out important data still has a low error rate.”
Lin US 20100070688 teaches “The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data.”
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-11 and 13-21 have received a first action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claim 12 has been canceled.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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October 7, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
