DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: "a plurality of scan units in a plurality of stages, respectively, wherein a respective scan circuit of the plurality of scan units comprises a first output terminal and a second output terminal in a respective stage … wherein the respective scan unit comprises at least one of an input subcircuit, a first processing subcircuit, a second processing subcircuit, or an output subcircuit; the respective scan unit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal" (emphasis added) in claim 5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner notes the claim as currently written does not provide sufficient structure to achieve the function as recited.
Therefore, the claim is being interpreted to include all the structure specifically disclosed in (1) Fig. 2 and paragraphs [0084]-[0107] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); (2) Fig. 6 and paragraph [0159] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); (3) Fig. 11 and paragraph [0163] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); (4) Fig. 12 and paragraph [0164] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); (5) Fig. 13 and paragraph [0165] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); (6) Fig. 14 and paragraph [00166] of the specification as filed (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections); and (7) claims 6-16 (embodiment specific connections for the subcircuits), respectively (enumeration added).
Additional support for this interpretation is found in claim 6 which recites a tenth transistor with no express prior recitation of first through ninth transistors other than the potential means plus function interpretation of claim 5.
In the interest of compact prosecution, Examiner notes the terms (1) input subcircuit; (2) first processing subcircuit; (3) second processing subcircuit; and (4) output subcircuit (see at least claim 5 – enumeration added) do not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because term circuit, combined with a description of the function of the circuit, connote sufficient structure to one of ordinary skill in the art (see MPEP §2181(I)(A)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Due to the claim interpretation of the term “scan unit” under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim 5 requires at least 15 transistors (M0-M14) and 3 capacitors (C1-C3). Subsequent recitation of duplicate structure for the pre-existing elements in claims 6-16 fail to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention and create antecedent basis problems.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over In (USPN 2023/0274687) in view of Higashida et al. (USPN 2009/0322718) and further in view of Li et al. (USPN 2006/0279205).
With respect to claim 1, In teaches a display apparatus (Figs. 1-31. At least Fig. 1 and paragraph [0071] teach a display), comprising:
a plurality of scan units in a plurality of stages, respectively, wherein a respective scan circuit of the plurality of scan units comprises a first output terminal and a second output terminal in a respective stage (Figs. 1-31. At least Figs. 11 and 12 and paragraphs [0225]-[0226]); and
a plurality of pixels (Figs. 1-31. At least Fig. 1, items PX and paragraph [0067]);
a pixel driving circuit configured to control light emission (Figs. 1-31. At least Fig. 1 and paragraph [0064] teach a driving transistor for a pixel);
wherein the pixel driving circuit is connected to the first output terminal and configured to receive the first and second control signals output from the first output terminal (Figs. 1 and 11-14 and paragraphs [0064]-[0074] and [0235]-[0235]).
However, In fails to expressly teach a light emitting substrate; a plurality of subpixels; wherein a respective subpixel of the plurality of subpixels comprises: a first light emitting element; a first pixel driving circuit configured to control light emission in the first light emitting element; a second light emitting element; and a second pixel driving circuit configured to control light emission in the second light emitting element; wherein the first light emitting element and the second light emitting element are configured to emit a light of a same color; wherein the first pixel driving circuit is connected to the first output terminal and configured to receive the first control signal output from the first output terminal; and the second pixel driving circuit is connected to the second output terminal and configured to receive the second control signal output from the second output terminal (Examiner notes In teaches pixels in general but doesn’t not go into any detail regarding pixel specific structure or subpixels).
Higashida teaches a known technique of a display including a light emitting substrate and a plurality of subpixels (Figs. 3-4C and paragraphs [0057]-[0082]).
In teaches a base process/product of a display including pixels which the claimed invention can be seen as an improvement in that the display includes a light emitting element. Higashida teaches a known technique of a display including a light emitting substrate and a plurality of subpixels that is comparable to the base process/product.
Higashida’s known technique of a display including a light emitting substrate and a plurality of subpixels would have been recognized by one skilled in the art as applicable to the base process/product of In and the results would have been predictable and resulted in a light emitting substrate and a plurality of subpixels which results in an improved process/product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
In in view of Higashida teach a display including subpixels. However, In in view of Higashida fail to expressly teach wherein a respective subpixel of the plurality of subpixels comprises: a first light emitting element; a first pixel driving circuit configured to control light emission in the first light emitting element; a second light emitting element; and a second pixel driving circuit configured to control light emission in the second light emitting element; wherein the first light emitting element and the second light emitting element are configured to emit a light of a same color; wherein the first pixel driving circuit is connected to the first output terminal and configured to receive the first control signal output from the first output terminal; and the second pixel driving circuit is connected to the second output terminal and configured to receive the second control signal output from the second output terminal.
Li teaches a known technique of a display including specific subpixel structure and driving circuits (Figs. 2-4E and paragraphs [0021]-[0028]). Specifically, Li teaches a plurality of subpixels (Figs. 2-4E and paragraphs [0082] teach a pixel includes subpixels); wherein a respective subpixel of the plurality of subpixels comprises: a first light emitting element (Figs. 2-4E and paragraph [0021] teach a first sub-pixel light emitting element); a first pixel driving circuit configured to control light emission in the first light emitting element (Figs. 2-4E and paragraph [0021] teach the first sub-pixel is driven by a first TFT); a second light emitting element (Figs. 2-4E and paragraph [0021] teach a second sub-pixel light emitting element); a second pixel driving circuit configured to control light emission in the second light emitting element (Figs. 2-4E and paragraph [0021] teach the second sub-pixel is driven by a second TFT).
In in view of Higashida teaches a base process/product of a display including subpixels which the claimed invention can be seen as an improvement in that a respective subpixel of the plurality of subpixels comprises: a first light emitting element; a first pixel driving circuit configured to control light emission in the first light emitting element; a second light emitting element; and a second pixel driving circuit configured to control light emission in the second light emitting element; wherein the first light emitting element and the second light emitting element are configured to emit a light of a same color; wherein the first pixel driving circuit is connected to the first output terminal and configured to receive the first control signal output from the first output terminal; and the second pixel driving circuit is connected to the second output terminal and configured to receive the second control signal output from the second output terminal. Li teaches a known technique of a display including specific subpixel structure and driving circuits that is comparable to the base process/product.
Li’s known technique of a display including specific subpixel structure and driving circuits would have been recognized by one skilled in the art as applicable to the base process/product of In in view of Higashida and the results would have been predictable and resulted in wherein a respective subpixel of the plurality of subpixels comprises: a first light emitting element; a first pixel driving circuit configured to control light emission in the first light emitting element; a second light emitting element; and a second pixel driving circuit configured to control light emission in the second light emitting element; wherein the first light emitting element and the second light emitting element are configured to emit a light of a same color; wherein the first pixel driving circuit is connected to the first output terminal and configured to receive the first control signal output from the first output terminal; and the second pixel driving circuit is connected to the second output terminal and configured to receive the second control signal output from the second output terminal which results in an improved process/product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
With respect to claim 2, In in view of Higashida and further in view of Li teach the display apparatus of claim 1, discussed above, further comprising a color filter substrate (Li, Fig. 2, item 22 and paragraph [0021]);
wherein the color filter substrate comprises:
a color conversion layer comprising a plurality of color conversion blocks (Li, Figs. 2 and 3C and paragraph [0036]); and
a color filter comprising a plurality of color filter blocks (Li, Fig. 2 and paragraph [0021]).
With respect to claim 3, In in view of Higashida and further in view of Li teach the display apparatus of claim 1, discussed above, wherein the first light emitting element and the second light emitting element are connected to a same data line (In, Fig. 1. Examiner notes the term “connected” is subject to a reasonably broad interpretation and includes indirect connections).
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record teaches stages of scan drivers including at least fifteen transistors and three capacitors (Figs. 12 and 21 and paragraph [0164] of In et al. USPN 2023/0351972; Fig. 3 of In et al. USPN 2023/0326388; Fig. 19 of In USPN 2023/0274687; Fig. 4 of Kim et al. USPN 2023/0186858; Fig. 8 of Chai et al. USPN 2023/0186849).
However, the prior art of record fails to teach or suggest the specific structure required by Applicant’s specific
“display apparatus of claim 1, wherein the first pixel driving circuit has a total number of transistors greater than the second pixel driving circuit” (claim 4); and
“scan unit” (claim 5 – emphasis added) as interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (i.e., transistors M0-M14 and capacitors C1-C3 and their specific inputs/outputs and connections as discussed above).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
In et al. (USPN 2023/0351972), In et al. (USPN 2023/0326388), In (USPN 2023/0274687), Kim et al. (USPN 2023/0186858) and Chai et al. (USPN 2023/0186849) teach stages of scan drivers including at least fifteen transistors and three capacitors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO J XAVIER whose telephone number is (571)270-7688. The examiner can normally be reached on M-F 830am-5pm PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO XAVIER/
Primary Examiner, Art Unit 2622