DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-15 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 05/30/2025 are acceptable for examination purposes.
Information Disclosure Statement
6. The references listed in the information disclosure statement (IDS) submitted on 05/30/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In regards to claim 1:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites a series of steps and, therefore, is a process, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generating a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits ---to the plurality of logical qubits in order to implement error correction operations, said generating comprises: selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section; selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section; and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits,” as drafted, is a process that, under the broadest reasonable interpretation , covers a mathematical relationship of the mathematical concept grouping. The terms of the claims are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. Thus, if a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls into the mathematical relationship as part of the mathematical grouping of abstract idea. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional element of “obtaining a logical representation” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities does not provide practical application.
At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “a quantum circuit” and “a quantum computer” are generic component that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Therefore, the claim is not patent eligible.
In regards to claim 8:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites an apparatus and, therefore, is a machine/manufacture and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “tthe logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits --- to the plurality of logical qubits in order to implement error correction operations, said generate comprises: selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section; selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section; and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits,” as drafted, is a process that, under the broadest reasonable interpretation , covers a mathematical relationship of the mathematical concept grouping. The terms of the claims are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. Thus, if a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls into the mathematical relationship as part of the mathematical grouping of abstract idea. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional elements of “obtain a logical representation” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities and does not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “quantum circuit,” “a quantum computer,” “a processor,” and “memory” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Therefore, the claim is not patent eligible.
In regards to claim 15:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites a computer program product and, therefore, is a machine/manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generate comprises: selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section; selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section; and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits,” as drafted, is a process that, under the broadest reasonable interpretation , covers a mathematical relationship of the mathematical concept grouping. The terms of the claims are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. Thus, if a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls into the mathematical relationship as part of the mathematical grouping of abstract idea. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional limitations of “obtaining a logical representation” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities and does not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “a computer program product,” “a non-transitory computer readable medium,” “processor,” “a quantum circuit,” and “a quantum computer” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Therefore, the claim is not patent eligible.
Dependent claims 2-7 and 9-14 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing the mathematical concept grouping. The dependent claims fail to integrate the abstract idea into a practical application rather they are mere instructions for performing the mathematical relationship of the mathematical concept grouping. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims 1-15 are not patent eligible.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
8. Claims 1-15 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-15 of U.S. Patent Application No. 12,340,278. This is a non-provisional statutory double patenting rejection since the claims directed to the same invention have in fact been patented. Therefore, the claims are anticipated by U.S. Patent Application No. 12,340,278 as shown in the chart and explanation below.
Instant Application No. 19/223,201
Patent Application No. US 12,340,278
Claim 1.
A method comprising: obtaining a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates;
and generating a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generating comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Claim 1.
A method comprising: obtaining a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates;
and generating a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generating comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Claim 2:
The method of claim 1, wherein said selecting comprises determining that the first and second quantities optimize values of the utility per-qubit metric for the first and second separate sections, respectively.
Claim 2:
The method of claim 1, wherein said selecting comprises determining that the first and second quantities optimize values of the utility per-qubit metric for the first and second separate sections, respectively.
Claim 3.
The method of claim 2, wherein said optimizing comprises implementing a search algorithm on a plurality of alternative physical representations of the first separate section of the quantum circuit, wherein the first separate section of the quantum circuit is implementable using the plurality of alternative physical representations, wherein each of the plurality of alternative physical representations comprises a different selected quantity of physical qubits for the first separate section, wherein the search algorithm is configured to search for an optimal utility per-qubit score of the first separate section in a solution space that comprises the plurality of alternative physical representations.
Claim 3.
The method of claim 2, wherein said optimizing comprises implementing a search algorithm on a plurality of alternative physical representations of the first separate section of the quantum circuit, wherein the first separate section of the quantum circuit is implementable using the plurality of alternative physical representations, wherein each of the plurality of alternative physical representations comprises a different selected quantity of physical qubits for the first separate section, wherein the search algorithm is configured to search for an optimal utility per-qubit score of the first separate section in a solution space that comprises the plurality of alternative physical representations.
Claim 4.
The method of claim 3, wherein the quality metric is monotonically correlated to error rates of the first separate section when implementing each alternative physical representation.
Claim 4.
The method of claim 3, wherein the quality metric is monotonically correlated to error rates of the first separate section when implementing each alternative physical representation.
Claim 5.
The method of claim 1, wherein the cost function of the first separate section is determined based on the first quantity of physical qubits and a quantity of cycles used by the first separate section.
Claim 5.
The method of claim 1, wherein the cost function of the first separate section is determined based on the first quantity of physical qubits and a quantity of cycles used by the first separate section.
Claim 6.
The method of claim 1, wherein said selecting comprises determining that the first quantity of physical qubits optimizes the utility per-qubit score of the first separate section while complying with a constraint on the quality score.
Claim 6.
The method of claim 1, wherein said selecting comprises determining that the first quantity of physical qubits optimizes the utility per-qubit score of the first separate section while complying with a constraint on the quality score.
Claim 7.
The method of claim 1, wherein said synthesizing the circuit according to the first and second quantities of physical qubits is estimated to provide an error rate of the quantum circuit, wherein said selecting is based on a marginal value of an error unit of the error rate.
Claim 7.
The method of claim 1, wherein said synthesizing the circuit according to the first and second quantities of physical qubits is estimated to provide an error rate of the quantum circuit, wherein said selecting is based on a marginal value of an error unit of the error rate.
Claim 8.
An apparatus comprising a processor and coupled memory, said processor being adapted to: obtain a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generate comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Claim 8.
An apparatus comprising a processor and coupled memory, said processor being adapted to: obtain a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generate comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Claim 9.
The apparatus of claim 8, wherein said selecting comprises determining that the first and second quantities optimize values of the utility per-qubit metric for the first and second separate sections, respectively.
Claim 9.
The apparatus of claim 8, wherein said selecting comprises determining that the first and second quantities optimize values of the utility per-qubit metric for the first and second separate sections, respectively.
Claim 10.
The apparatus of claim 9, wherein said optimizing comprises implementing a search algorithm on a plurality of alternative physical representations of the first separate section of the quantum circuit, wherein the first separate section of the quantum circuit is implementable using the plurality of alternative physical representations, wherein each of the plurality of alternative physical representations comprises a different selected quantity of physical qubits for the first separate section, wherein the search algorithm is configured to search for an optimal utility per-qubit score of the first separate section in a solution space that comprises the plurality of alternative physical representations.
Claim 10.
The apparatus of claim 9, wherein said optimizing comprises implementing a search algorithm on a plurality of alternative physical representations of the first separate section of the quantum circuit, wherein the first separate section of the quantum circuit is implementable using the plurality of alternative physical representations, wherein each of the plurality of alternative physical representations comprises a different selected quantity of physical qubits for the first separate section, wherein the search algorithm is configured to search for an optimal utility per-qubit score of the first separate section in a solution space that comprises the plurality of alternative physical representations.
Claim 11.
The apparatus of claim 10, wherein the quality metric is monotonically correlated to error rates of the first separate section when implementing each alternative physical representation.
Claim 11.
The apparatus of claim 10, wherein the quality metric is monotonically correlated to error rates of the first separate section when implementing each alternative physical representation.
Claim 12.
The apparatus of claim 8, wherein the cost function of the first separate section is determined based on the first quantity of physical qubits and a quantity of cycles used by the first separate section.
Claim 12.
The apparatus of claim 8, wherein the cost function of the first separate section is determined based on the first quantity of physical qubits and a quantity of cycles used by the first separate section.
Claim 13.
The apparatus of claim 8, wherein said selecting comprises determining that the first quantity of physical qubits optimizes the utility per-qubit score of the first separate section while complying with a constraint on the quality score.
Claim 13.
The apparatus of claim 8, wherein said selecting comprises determining that the first quantity of physical qubits optimizes the utility per-qubit score of the first separate section while complying with a constraint on the quality score.
Claim 14.
The apparatus of claim 8, wherein said synthesizing the circuit according to the first and second quantities of physical qubits is estimated to provide an error rate of the quantum circuit, wherein said selecting is based on a marginal value of an error unit of the error rate.
Claim 14.
The apparatus of claim 8, wherein said synthesizing the circuit according to the first and second quantities of physical qubits is estimated to provide an error rate of the quantum circuit, wherein said selecting is based on a marginal value of an error unit of the error rate.
Claim 15.
A computer program product comprising a non-transitory computer readable medium retaining program instructions, which program instructions, when read by a processor, cause the processor to: obtain a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates;
and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generate comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity,
wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Claim 15.
A computer program product comprising a non-transitory computer readable medium retaining program instructions, which program instructions, when read by a processor, cause the processor to: obtain a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates;
and generate a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations, said generate comprises:
selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section, wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity,
wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section;
selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section, wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section;
and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits.
Reasons for Allowance
9. Claims 1-15 are allowed once the claim rejections -35 USC § 101 and double patenting rejections are overcome. The following is an examiner’s statement of reasons for allowance:
As per claim 1:
Particularly the prior art of record, and in particular SCHUSTER et al. (US 2022/0156630 A1), teach a method comprising: obtaining a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates (see paragraph [0077], and Figs.1- 3); and generating a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations said generating comprises (see paragraph [0075], and Figs.1-3): selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit, wherein said selecting is based on a utility per-qubit metric that is used to define a utility per-qubit score of the first separate section, wherein the utility per-qubit score of the first separate section indicates a utility of each qubit in the first separate section (see paragraph [0078], and Figs.1-3).; selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, the first and second quantities are different, the first and second separate sections are disjoint sections of the quantum circuit, wherein said selecting is based on a utility per-qubit score of the second separate section that indicates a utility of each qubit in the second separate section; and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections, wherein a quantity of the set of physical qubits is greater than a quantity of the plurality of logical qubits (see paragraph [0078], and Figs.1-3).
The prior arts however are not concerned with and do not teach, suggest, or otherwise render obvious “wherein the utility per-qubit score of the first separate section is determined based on a ratio between a quality score of the first separate section when using the first quantity and between a cost function of the first separate section when using the first quantity, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of the first separate section; ---- and wherein the utility per-qubit score of the second separate section is determined based on a ratio between a quality score of the second separate section when using the second quantity and between a cost function of the second separate section when using the second quantity, wherein the quality score is monotonically correlated to error rates of the second separate section” as taught by claim 1. Hence the prior art taken alone or in any combination fail to teach the claimed novel feature in claim 1.
In regards to independent claims 8 and 15:
The claims include similar limitations of independent claim 1. Therefore, are allowed for similar reason of claim 1 above.
Dependent claims 2-7 and 9-14 depend from the base claims 1 and 8 respectively and inherently include limitations therein and therefore are allowed as well.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Examiner Notes
10. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
11. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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