Claim Objections
Claim 1 is objected to because of the following informalities: “second control node” in lines 12 and 17, should be --third control node-- . Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/577,408 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Although the conflicting claims are not identical, they are not patentably distinct from each other because:
The patent claims include all of the limitations of the instant application claims, respectively. The patent claims also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims. As such, the instant application claims are anticipated by the patent claims and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
19223219
1.A driving circuit, comprising a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit;
wherein the driving signal generation circuit is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of a first control node and a potential of a second control node; the gating circuit is electrically connected to a first node and a gating input terminal respectively;
the output control circuit is electrically connected to the first node, the first control node and a second node respectively, and is configured to control to connect the first control node and the second node under the control of the potential of the first node; the voltage control circuit is electrically connected to the first node; the output circuit is electrically connected to the second node, the second control node, a first voltage terminal, a second voltage terminal and a output driving terminal respectively, and is configured to control to connect the output driving terminal and the first voltage terminal under the control of a potential of the second node, and control to connect the output driving terminal and the second voltage terminal under the control of a potential of the second control node;
N is a positive integer.
18/577408
1.A driving circuit, comprising a driving signal generation circuit, an output control circuit, a gating circuit, a voltage control circuit, an output circuit connected to a first node, the first control node and a second node respectively, and is configured to control to connect the first control node and the second node under the control of a potential of the first node; the gating circuit is electrically connected to a gating control terminal, a gating input terminal and the first node respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first node under the control of a gating control signal provided by the gating control terminal; the voltage control circuit is electrically connected to the first node and the second node respectively, and is configured to control a potential of the second node according to the potential of the first node; the output circuit is electrically connected to the second node, a third control node, and an Nth stage of output driving terminal respectively, and is configured to generate and output an Nth stage of output driving signal through the Nth stage of output driving terminal under the control of the potential of the second node and a potential of the third control node; the third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.
Allowable Subject Matter
Claims 1-20 are allowable if overcome the double patenting rejection above.
Huang et al. US 2022/034828, fig. 14, discloses The third node control circuit is respectively electrically connected to a first clock signal terminal, a second clock signal terminal, an input terminal and a third node, and is configured to connect or disconnect the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal; The second node control circuit is respectively electrically connected with the second node, the second voltage terminal, a fourth node, a third clock signal terminal and a control node, and is configured to control to connect or disconnect the control node and the second voltage terminal under the control of the potential of the fourth node, and control to connect or disconnect the control node and the third clock signal terminal under the control of the potential of the second node, and control the potential of the second node according to the potential of the control node; The fourth node control circuit is respectively electrically connected to the first voltage terminal, the second clock signal terminal, the fourth node and the third node, and is configured to control to connect or disconnect the fourth node and the first voltage terminal under the control of the second clock signal, and control to connect or disconnect the fourth node and the second clock signal terminal under the control of the potential of the third node.
Zhang US 20240321161, figs. 11, 19, The third node control circuit is respectively electrically connected to a first clock signal terminal, a second clock signal terminal, an input terminal and a third node, and is configured to connect or disconnect the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal; The second node control circuit is respectively electrically connected with the second node, the second voltage terminal, a fourth node, a third clock signal terminal and a control node, and is configured to control to connect or disconnect the control node and the second voltage terminal under the control of the potential of the fourth node, and control to connect or disconnect the control node and the third clock signal terminal under the control of the potential of the second node, and control the potential of the second node according to the potential of the control node; The fourth node control circuit is respectively electrically connected to the first voltage terminal, the second clock signal terminal, the fourth node and the third node, and is configured to control to connect or disconnect the fourth node and the first voltage terminal under the control of the second clock signal, and control to connect or disconnect the fourth node and the second clock signal terminal under the control of the potential of the third node;
None of the references cited in record disclose or suggest that 1.A driving circuit, comprising a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit; wherein the driving signal generation circuit is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of a first control node and a potential of a second control node; the gating circuit is electrically connected to a first node and a gating input terminal respectively; the output control circuit is electrically connected to the first node, the first control node and a second node respectively, and is configured to control to connect the first control node and the second node under the control of the potential of the first node; the voltage control circuit is electrically connected to the first node; the output circuit is electrically connected to the second node, the second control node, a first voltage terminal, a second voltage terminal and a output driving terminal respectively, and is configured to control to connect the output driving terminal and the first voltage terminal under the control of a potential of the
Conclusion
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/VAN N CHOW/Primary Examiner, Art Unit 2627