Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/30/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 of U.S. Patent No. 12,340,088. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the Patent would anticipate those of the current application.
19/223,296
12,340,088
1. A memory device comprising:
a plurality of command-and-address (CA) samplers configured to receive, as a
plurality of first CA signals, a command comprising a predetermined pattern, via a CA
bus, based on an exit of a sleep mode before the memory device enters a CA training
mode, wherein the plurality of CA samplers are further configured to sample the
plurality of first CA signals, respectively; and
a command decoder configured to:
check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers, and enter the CA training mode based on the parity error occurring in the
plurality of first CA signals.
1. A memory device comprising:
a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers is further configured to sample a corresponding first CA signal among the plurality of first CA signals; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers,
wherein the plurality of CA samplers are further configured to:
receive a first row-no-operation (RNOP) command and a first column-no- operation (CNOP) command as a plurality of second CA signals before receiving the command comprising the predetermined pattern; and
receive a second RNOP command and a second CNOP command as a plurality of third CA signals after receiving the command comprising the predetermined pattern.
9. The memory device of claim 1, wherein the command decoder is further configured to enter a CA training mode based on the parity error occurring in the plurality of first CA signals.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 10-18 of U.S. Patent No. 12,340,088 in view of Chaudhuri et al. (US 2011/0320867).
US Patent 12,340,088 does not expressly disclose entering a training mode based on the parity error occurring in the plurality of first CAS signals.
Chaudhuri discloses a method and an apparatus for training a command-address (C/A) memory signal [see paragraph 1]. A training mode may be entered based on the parity error occurring in the plurality of first CAS signals [see paragraph 24].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the training mode entrance sequence of Chaudhuri.
The motivation for doing so would have been to begin to train the C/A signal without initiating a reboot of the memory system or a JEDEC standardized initialization process [see Chaudhuri, paragraph 24].
Therefore, it would have been obvious to combine Chaudhuri with US Patent 12,340,088 for the benefits listed above, to obtain the invention as specified in claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-10 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bloemer et al. (US 2022/0246183) in view of Chaudhuri et al. (US 2011/0320867).
Regarding claim 1, Bloemer discloses a memory device comprising:
a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus [see paragraphs 5-6 & 32-35; during CA bus training, patterns are sent from memory controller to DRAM storage device] based on an exit of a sleep mode [see paragraphs 42-43; pattern may be applied upon powering up or exiting a low power state], wherein each of the plurality of CA samplers is further configured to sample a corresponding first CA signal among the plurality of first CA signals ; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers [see paragraphs 5-6 & 32-35; pattern is checked at DRAM and compared to expected pattern to determine if an error has occurred].
Bloemer does not expressly disclose entering a training mode based on the parity error occurring in the plurality of first CAS signals.
Chaudhuri discloses a method and an apparatus for training a command-address (C/A) memory signal [see paragraph 1]. A training mode may be entered based on the parity error occurring in the plurality of first CAS signals [see paragraph 24].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the training mode entrance sequence of Chaudhuri.
The motivation for doing so would have been to begin to train the C/A signal without initiating a reboot of the memory system or a JEDEC standardized initialization process [see Chaudhuri, paragraph 24].
Therefore, it would have been obvious to combine Chaudhuri with Bloemer for the benefits listed above, to obtain the invention as specified in claims 1, 6-10 and 15-19.
Regarding claim 6, the combination discloses the memory device of claim 1, wherein the predetermined pattern comprises a pattern for testing the CA bus [see Bloemer, paragraphs 5-7; pattern is used for training (testing) the CA bus].
Regarding claim 7, the combination discloses the memory device of claim 1, wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals toggle from a high level to a low level or from the low level to the high level [see Bloemer, paragraphs 32-35; patterns may be a pseudo random binary sequence (i.e. the CA signals would toggle from high to low randomly)].
Regarding claim 8, the combination discloses the memory device of claim 1, wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have high levels over a plurality of consecutive clock cycles, and subsequently, change to low levels [see Bloemer, paragraphs 32-35; patterns may be a pseudo random binary sequence (i.e. the CA signals would toggle from high to low randomly)].
Regarding claim 9, the combination discloses the memory device of claim 1, wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have low levels over a plurality of consecutive clock cycles, and subsequently, change to high levels [see Bloemer, paragraphs 32-35; patterns may be a pseudo random binary sequence (i.e. the CA signals would toggle from low to high randomly)].
Regarding claim 10, the combination discloses the memory device of claim 1, wherein the command decoder is further configured to enter a CA training mode based on the parity error occurring in the plurality of first CA signals [see Bloemer, paragraph 35; adjustments may be made to transmission and reception of signals based on the patterns not matching (error)].
Claims 11 and 16-19 recite similar claim limitations as claims 1 and 6-10 above and are rejected using the same citations and interpretations.
Allowable Subject Matter
Claims 2-5 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the Double Patenting rejections are properly overcome. Though the prior art of record discloses training a CA bus to fix timing errors, it fails to teach or render obvious the claim limitations regarding the sending of column and row no operation signals prior to and after the pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lovelace et al. (US 2019/0034365), Jue et al. (US 2019/0042519), Huo et al. (US 10,203,875) -
Disclose training the timing of a command/address bus using patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137
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