CTNF 19/223,316 CTNF 82116 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is responsive to the application filed 30 May 2025. Claims 1-20 are pending and have been presented for examination. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1, 2, 4, 5, 8-10, 12, 14, 15 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 2, 4-9, 11, 12 and 14 of U.S. Patent No. 12,333,160 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘160 patent as shown below . 12,333,160 19/223,316 1. A memory device, comprising: one or more components configured to: (A) identify a voltage pattern to be used to execute a read command, to read data stored by the memory device, based on a type of the read command, (B) wherein a first voltage pattern is identified if the type of the read command is a first type and a second voltage pattern is identified if the type of the read command is a second type, wherein the second voltage pattern is different from the first voltage pattern, (C) and wherein: the second voltage pattern consumes less power than the first voltage pattern, or the second voltage pattern is associated with a longer read time than the first voltage pattern; (D) and apply the identified voltage pattern to perform a read operation based on the read command, (E) wherein the first voltage pattern is applied if the type of the read command is the first type and the second voltage pattern is applied if the type of the read command is the second type. 1. A memory device, comprising: one or more components configured to: (A) identify a voltage pattern to be used to execute a read command, to read data stored by the memory device, based on a type of the read command, (A) wherein: a first voltage pattern is identified if the type of the read command is a first type and a second voltage pattern is identified if the type of the read command is a second type, (C) and the second voltage pattern consumes less power than the first voltage pattern or the second voltage pattern is associated with a longer read time than the first voltage pattern; (D) and apply the identified voltage pattern to perform a read operation based on the read command, (E) wherein the first voltage pattern corresponds to a first type of read operation and the second voltage pattern corresponds to a second type of read operation. Claims 5/4/6/2/7 Claims 2/4/5/8/9 8. A method, comprising: (A) detecting, by a memory device, a read command associated with reading data stored by the memory device; (B) selecting, by the memory device and based on a type of the read command, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, (C) wherein the first voltage pattern is selected if the type of the read command is a first type and the second voltage pattern is selected if the type of the read command is a second type, wherein the second voltage pattern is different from the first voltage pattern , and wherein: (D) the second voltage pattern consumes less power than the first voltage pattern, or the second voltage pattern is associated with a longer read time than the first voltage pattern; (E) and executing, by the memory device, the read command using the selected one of the first voltage pattern or the second voltage pattern. 10. A method, comprising: (A) detecting, by a memory device, a read command associated with reading data stored by the memory device; (B) selecting, by the memory device and based on a type of the read command, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, (C) wherein: a first voltage pattern is identified if the type of the read command is a first type and a second voltage pattern is identified if the type of the read command is a second type, (D) and the second voltage pattern consumes less power than the first voltage pattern or the second voltage pattern is associated with a longer read time than the first voltage pattern; (E) and executing, by the memory device, the read command using the selected one of the first voltage pattern or the second voltage pattern. Claims 12/11/13/9/14 Claims 12/14/15/18/19 1. A memory device, comprising: one or more components configured to: (A) identify a voltage pattern to be used to execute a read command, to read data stored by the memory device, based on a type of the read command, wherein: a first voltage pattern is identified if the type of the read command is a first type and a second voltage pattern is identified if the type of the read command is a second type, (B) and the second voltage pattern consumes less power than the first voltage pattern or the second voltage pattern is associated with a longer read time than the first voltage pattern; (D) and apply the identified voltage pattern to perform a read operation based on the read command, (C) wherein the first voltage pattern corresponds to a first type of read operation and the second voltage pattern corresponds to a second type of read operation. 20. A system, comprising: (A) means for selecting a voltage pattern from a set of voltage patterns that includes a first voltage pattern and a second voltage pattern, to be applied to memory cells of a memory device during a read operation, based on a type of the read operation, (B) wherein: the second voltage pattern consumes less power than the first voltage pattern or the second voltage pattern is associated with a longer read time than the first voltage pattern, (C) and the first voltage pattern corresponds to a first type of read operation and the second voltage pattern corresponds to a second type of read operation; (D) and means for applying the selected voltage pattern to the memory cells to perform the read operation . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3, 6, 7, 11, 13, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the independent claims of the instant application are commensurate in scope with the ‘160 patent and are therefore distinct from the prior are for the same reasons. The additional limitations in dependent claims 3, 6, 7, 11, 13, 16 and 17 simply add to claims that are already distinct from the prior art . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 2019/0286518: discloses host generated read commands and memory device generated read commands, selecting a voltage pattern based on the type of read and applying the voltage pattern for a read operation (see [0077]-[0079], [0082]-[0084], [0107]). 2023/0251781: discloses read operations that utilize different voltages based on the type of read (see [0033]-[0037]). 2023/0153201: discloses read command with different read levels, the different read levels are used by the controller to perform error detection and correction (see [0040], [0080]-[0085]). 2022/0222138: discloses a host read, and when the host read fails the controller generates another read with a different voltage (see [0036]). 2022/0147275: discloses selecting a voltage to use based on the type of command received (see [0060]). 2021/0311830: discloses changing a read mode when a read fails, controller generates a read command and a read retry voltage is used for the generated read (see [0040]-[0050]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain T Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132 Application/Control Number: 19/223,316 Page 2 Art Unit: 2132 Application/Control Number: 19/223,316 Page 3 Art Unit: 2132 Application/Control Number: 19/223,316 Page 4 Art Unit: 2132 Application/Control Number: 19/223,316 Page 5 Art Unit: 2132 Application/Control Number: 19/223,316 Page 6 Art Unit: 2132 Application/Control Number: 19/223,316 Page 7 Art Unit: 2132 Application/Control Number: 19/223,316 Page 8 Art Unit: 2132 Application/Control Number: 19/223,316 Page 9 Art Unit: 2132 Application/Control Number: 19/223,316 Page 10 Art Unit: 2132 Application/Control Number: 19/223,316 Page 11 Art Unit: 2132 Application/Control Number: 19/223,316 Page 12 Art Unit: 2132 Application/Control Number: 19/223,316 Page 13 Art Unit: 2132 Application/Control Number: 19/223,316 Page 14 Art Unit: 2132 Application/Control Number: 19/223,316 Page 15 Art Unit: 2132 Application/Control Number: 19/223,316 Page 16 Art Unit: 2132 Application/Control Number: 19/223,316 Page 17 Art Unit: 2132 Application/Control Number: 19/223,316 Page 18 Art Unit: 2132
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