DYNAMIC WEAR RATIO MANAGEMENT

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION As per the instant application having Application No. 19/223,389, the amendment filed on 9/8/2026 is herein acknowledged. Claims 1, 3, 5, 8, 10, 12, 15 and 18 have been amended. Claims 1-20 are pending. In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. CLAIM CONSTRUCTION The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II). See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original. Note that the limitations “in response to” (in method claims 9, 13-14) may never be reached within the scope of the claim under the broadest reasonable interpretation since the condition to which the “in response to” statement is subject may never occur within the scope of the claim. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II). It is suggested method claims 9 and 13-14 be amended to first require the condition to which the “in response to” statement is subject to occur and then in response to the condition occurring, performing the rest of the limitations. For example, claim 9 should be amended to read “determining an erase operation is being performed on the block; updating, in response to the erase operation being performed on the block,…”. Additionally, note that apparatus claims 16 and 19-20 have been written as a hybrid claims which recite both a non-transitory computer readable storage medium in the preamble and method steps “within the body of the claim that also contain contingent limitations. It is suggested claims 16 and 19-20 be amended in the same manner as claim 9. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 7-12, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220398040 A1) in view of Neufeld et al. (US 20200004671) and Ionin et al. (US 2023/0162808). 1. A system, comprising: a memory device; and [Kang teaches memory device 100 (fig. 1 and related text)] a processing device operatively coupled to the memory device, the processing device to perform operations, comprising: performing a program operation on a block of the memory device; [Kang teaches “[0049] For example, the operation controller 210 may control the memory device 100 to perform the write operation on the selected memory block among the plurality of memory blocks according to a write request received from the host 300.”] retrieving, from a metadata structure associated with a block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device; [Kang teaches “[0094] Referring to FIG. 4, the memory block may include the main area storing user data and the spare area storing meta information. The meta information may be information for managing the user data and may include mapping information, erase and write count information, read count information, the lifetime information…” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.”], thus, using erase count as well as type information; where count information and lifetime information (which includes maximum erase counts for different block types) and thus reflects a type of the block are retrieved from the meta information are or metadata structure of the memory block determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and [Kang teaches “[0052] The lifetime information controller 220 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block (thus including both erase count and write operation count to determine lifetime information).” “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text)] updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function. [0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value. [0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.” “ The operation controller 210 may control the memory device 100 to store write data corresponding to the write request and the lifetime information including the lifetime level of the selected memory block in the selected memory block. The memory device 100 may store the write data in a main area of the selected memory block and store the lifetime information in a spare area.” (par. 0049) “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” “[0107] In FIG. 6, the lifetime level of the memory block may be determined to be between 1 and N, where N is a natural number greater than or equal to 2, N representing the greatest lifetime level, which is predetermined. The alert level may be K, where K is a natural number greater than 1 and less than or equal to N. When the lifetime level of the memory block is greater than or equal to the alert level, the storage device may provide the flag indicating that the lifetime of the memory block is in the alert state to the host.” “[0111] The lifetime level of the memory block may determine a lifetime level corresponding to a section to which the erase and write count of the memory block belongs among the plurality of sections included in the lifetime level table. In an embodiment, the largest reference value Ref_N−1 among the plurality of reference values Ref_1 to Ref_N−1 may be the maximum erase and write count of the memory block.” (figs. 6 and 7 and related text)] where the alert level for the block determined according to lifetime level of the memory block determined according to the remaining program erase cycles for the memory block is updated and represents a media endurance metric value; however, Kang does not expressly refer to the wear ratio or lifetime level of the memory block used to update an endurance metric value; however, regarding these limitations, Neufeld teaches [“[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.” “[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.” Thus, using the wear ratio or rate of P/E cycles for the different memory types to update an expected EOL, which corresponds to the media endurance metric value for each of the memory types]. Kang and Neufeld are analogous art because they are from the same field of endeavor of memory access and control. Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of Kang to explicitly use the lifetime level or wear ratio which includes the number of P/E cycles for the different types of memory blocks to calculate an end of life estimate or media endurance metric for each of the memory types as taught by Neufeld since doing so would provide the benefits of [“ In some embodiments, as the memory device continues in operation, the controller and/or host can monitor usage to determine whether to reconfigure the memory device to change the amount of memory assigned to the high endurance section. For example, if the usage patterns suggest more high endurance memory is needed, some of the MLC memory section could be switched to SLC operation and added to the high endurance memory section.” (par. 0054) thus optimizing the memory’s lifetime (par. 0002)]. The combination of Kang and Neufeld does not expressly disclose wherein a plurality of erase operations of different memory cell types are performed on the block during a single program-erase cycle (PEC) prior to the program operation; however, regarding these limitations, Ionin teaches [“[0048] At block 502, the controller 108 allocates a TLC block. At block 504, the controller 108 determines if the next hybrid block is pre-erased (e.g., SLC pre-erased, TLC pre-erased, or inconclusive). If the next hybrid block is not TLC erased at block 504, then the controller 108 TLC erases the next hybrid block at block 506. At block 510, the controller 108 writes to the TLC erased block. However, if the next hybrid block is pre-erased at block 504, then the controller 108 re-erases the next hybrid block as a TLC block in order to avoid programming TLC data to an SLC erased block at block 508. At block 510, the controller 108 writes to the TLC erased block. In some cases, external conditions, such as abnormal temperature changes or conditions causing high BER, may cause the controller 108 to allocate a higher than expected amount of hybrid blocks as TLC blocks.”, thus having an SLC pre-erase operation and a TLC erase operation before writing to the TLC bock or during a single PEC cycle prior to the program operation]. Kang, Neufeld and Ionin are analogous art because they are from the same field of endeavor of memory access and control. Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of the combination of Kang and Neufeld to include wherein a plurality of erase operations of different memory cell types are performed on the block during a single program-erase cycle (PEC) prior to the program operation, as taught by Ionin, since doing so would provide the benefits of [ensuring a block is properly erased before performing a program operation where “a violation of SLC programming over a TLC erased block may be avoided. Furthermore, blocks in a non-pre-erased heap are erased based on the next program operation type. For example, a block that is to be used for a SLC operation will be SLC erased prior to programming the block with TLC data and a block that is to be used for a TLC operation will be TLC erased prior to programming the block with TLC data.” (par. 0044)]. Therefore, it would have been obvious to combine Kang and Neufeld with Ionin for the benefit of creating a storage system/method to obtain the invention as specified in claim 1. 2. The system of claim 1, wherein the operations further comprise: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [Kang teaches “[0052] The lifetime information controller 220 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block (thus including both erase count and write operation count to determine lifetime information).” “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” Kang teaches “[0094] Referring to FIG. 4, the memory block may include the main area storing user data and the spare area storing meta information. The meta information may be information for managing the user data and may include mapping information, erase and write count information, read count information, the lifetime information…” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text). Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.” “[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.”]. 3. The system of claim 1, wherein the wear ratio represents a relationship between a first number of program-erase cycles (PECs) of a first erase-program scheme that causes a first amount of cell damage to a block and a second number of PECs of a second erase-program scheme that causes a second amount of cell damage to a block, wherein a difference between the first amount of cell damage and the second amount of cell damage is less than a predefined threshold [Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days. [0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613. [0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711…” (thus, the difference between the wear or damage of the first type of memory and second type of memory may be found to be less than a threshold)]. 4. The system of claim 1, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the operations further comprise: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711… [0061] Returning to FIG. 8, at step 711 the host is alerted to the EOL imbalance. If either the SLC section 613 or the MLC section 611 is aging relatively rapidly, the host may decide to reconfigure the memory. Continuing with the above example, the high endurance SLC section 613 is being heavily written and the host may decide to transfer some of the MLC section 611 to the high endurance SLC section 613, subsequently operating memory cells of the transferred portion in SLC mode. The host may also have additional information, such as information indicating that high usage rate of the high endurance section 613 is temporary and decide not to reconfigure at this time. If the host decides to reconfigure the memory at step 713, the host's reply to the memory system requests such a reconfiguration, which is executed at step 715 before looping back to step 705. If the memory is not to be reconfigured, the flow loops back from step 713 to step 705 for continued operation without reconfiguring the memory… [0080] At step 921, the relative wear levels of the sections are checked to see whether one of these areas is approaching its End Of Life (EOL) more rapidly than another. For example, even though the SLC section 813 has a higher endurance level than the MLC section 811, it may still be undergoing very intense write rates, so that it is nearing its EOL while the MLC section 811 is still relatively fresh. If the different memory sections are aging in a relatively balanced manner, such as the variation in their EOL values varying less than some threshold (No path), the flow continues back to 909. If, instead an imbalance is found (Yes path), the controller 802 informs the host 820 at step 923. The controller 802 receives the reply from host 820 at step 925 and, if a reconfiguration is requested, the controller 802 reconfigures the memory device 804 at step 927, transferring some of the memory cells of MLC section 811 to SLC section 813, or from SLC section 813 to MLC section 811, as requested by the host. After step 927 the flow then loops back to 909.”]. 5. The system of claim 1, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first program-erase cycle (PEC) [Kang teaches “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block (where erase and write counts correspond to a first PEC) into a lifetime level function including a maximum erase and write count of the memory block.” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text). Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.”]. 7. The system of claim 1, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [Kang teaches “Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function. [0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value. [0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.” Where indicating alert to the host continues to use the memory block. Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705 (where on looping back, the block continues to be allocated for use). If the difference is above the threshold, the imbalance is reported out to the host at step 711.”]. 8. A method, comprising: performing, by a processing device, a program operation on a block of a memory device; retrieving, from a metadata structure associated with the block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device, wherein a plurality of erase operations of different memory cell types are performed on the block during a single program-erase cycle (PEC) prior to the program operation; determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [The rationale in the rejection of claim 1 is herein incorporated]. 9. The method of claim 8, further comprising: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [The rationale in the rejection of claim 2 is herein incorporated]. 10. The method of claim 8, wherein the wear ratio represents a relationship between a first number of program-erase cycles (PECs) of a first erase-program scheme that causes a first amount of cell damage to a block and a second number of PECs of a second erase-program scheme that causes a second amount of cell damage to a block, wherein a difference between the first amount of cell damage and the second amount of cell damage is less than a predefined threshold [The rationale in the rejection of claim 3 is herein incorporated]. 11. The method of claim 8, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the method further comprises: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [The rationale in the rejection of claim 4 is herein incorporated]. 12. The method of claim 8, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first program-erase cycle (PEC) [The rationale in the rejection of claim 5 is herein incorporated]. 14. The method of claim 8, further comprising: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [The rationale in the rejection of claim 7 is herein incorporated]. 15. A non-transitory computer-readable storage medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising: performing a program operation on a block of a memory device; retrieving, from a metadata structure associated with the block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device, wherein a plurality of erase operations of different memory cell types are performed on the block during a single program-erase cycle (PEC) prior to the program operation; determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [The rationale in the rejection of claim 1 is herein incorporated]. 16. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [The rationale in the rejection of claim 2 is herein incorporated]. 17. The non-transitory computer-readable storage medium of claim 15, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the operations further comprise: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [The rationale in the rejection of claim 4 is herein incorporated]. 18. The non-transitory computer-readable storage medium of claim 15, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first program-erase cycle (PEC) [The rationale in the rejection of claim 5 is herein incorporated]. 20. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [The rationale in the rejection of claim 7 is herein incorporated]. Claims 6, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220398040 A1) in view of Neufeld et al. (US 20200004671) and Ionin et al. (US 2023/0162808) as applied in the rejection of claims 1, 8 and 15 above, and further in view of Barndt et al. (US 10282111). 6. The system of claim 1, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and [Kang teaches “Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function. [0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value. [0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.” Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711.”] but the combination does not expressly disclose retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device; however, regarding these limitations, Barndt teaches [“ The expected remaining number of cycles for a given block may be determined by subtracting the current cycle count for the block from the expected cycle count for the block. The subject system determines when the expected remaining number of cycles in a block of a given set of blocks is falling behind the expected remaining number of cycles of other blocks of the given set of blocks. In this instance, the subject system marks the block as temporarily inactive whichretir prevents the block from being utilized in the data storage operations…” (col. 4, lines 8-26) “ The blocks 202A-P may each be associated with a status that may be, for example, stored by the controller 114 in the RAM 122. The status of the blocks may include, for example, active blocks, retired blocks, manufacturer bad blocks (MBBs), grown bad blocks (GBBs), or temporarily inactive blocks, which may also be referred to as on vacation blocks (OVBs). Blocks that are active may be available for data storage operations (e.g. reading/writing); however, blocks that are retired, MBBs, GBBs, or temporarily inactive may not be available for data storage operations. In FIG. 2, the blocks 202B,G,H,N that are shaded are blocks that are temporarily inactive and therefore are not available for data storage operations.” (col. 7, line 63-col.8, line 8) “Prior to performing any data storage operations on the flash memory circuits 112A-N, the controller 114 selects the first flash memory circuit 112A of the flash memory device 110 (402). The controller 114 performs rapid program/erase (P/E) cycles on one block 202A from the first flash memory circuit 112A until a quality metric associated with the block 202A falls below a minimum quality level (404). The quality metric may be, for example, RBER, error count, program time, etc. The controller 114 then marks the block 202A as inactive, or retired, such that the block 202A will not be available for data storage operations (406).” (col. 10, lines 14-24)]. Kang, Neufeld, Ionin and Barndt are analogous art because they are from the same field of endeavor of memory access and control. Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of the combination of Kang, Neufeld and Ionin to include in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device as taught by Barndt since doing so would provide the benefits of [extending the life of the memory and allowing for evening the wear of memory blocks]. Therefore, it would have been obvious to combine Kang and Neufeld and Ionin with Barndt for the benefit of creating a storage system/method to obtain the invention as specified in claim 6. 13. The method of claim 8, further comprising: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device [The rationale in the rejection of claim 6 is herein incorporated]. 19. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device [The rationale in the rejection of claim 6 is herein incorporated]. RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Muchherla et al. (US 20190267105) teaches “[0040] In a number of embodiments, various trim settings corresponding to mixed mode operation can be adjusted to achieve a particular wear ratio of SLC operation wear to XLC operation wear. Trim settings that can be adjusted can include various write trims and/or erase trims. For example, write trims can include a program start voltage, program verification voltage(s), and program step voltage(s), among others. Erase trims can include an erase verify voltage, for example, which can be adjusted to result in a shallow erase. Adjustments to SLC mode trim settings, such as reducing the program start voltage, program verify voltage, and/or step voltage can reduce the wear experienced by the mixed mode blocks due to SLC operation, which can help to increase the wear ratio. Additionally, the SLC mode erase verify voltage can be reduced (e.g., such that it has a smaller magnitude), which can also reduce the wear due to the SLC mode erase and help to increase the wear ratio. In a number of embodiments, the adjusted SLC trim settings may be applied only to mixed mode blocks that are to be written in SLC mode. For example, it may not be beneficial to perform a shallow erase operation on a mixed mode block to be written in XLC mode since the shallow erase may have an effect on the accuracy of XLC writing. [0041] In one or more embodiments the mixed mode cycle count can be determined according to a relationship: [00001]((S)+(WR×X))WR, wherein “S” is a determined quantity of SLC mode cycles (e.g., erases), “X” is a determined quantity of XLC mode cycles (e.g., erases), and “WR” is a wear ratio of SLC operation wear to XLC operation wear. In a number of embodiments, a cycle count increment factor can be in associated with incrementing the effective cycle count. As an example, if the cycle count increment factor is “1”, then the count of the effective cycle count counter is incremented by 1 for each actual SLC mode cycle and by 2 for each actual XLC mode cycle (e.g., for WR=2). However, if the cycle count increment factor is “10”, then the count of the effective cycle count counter is incremented by 10 for each actual SLC mode cycle and by 20 for each actual XLC mode cycle. Providing a cycle count increment factor of 10 can provide benefits such as avoiding the need to perform floating point operations, which may occur in instances in which the wear ratio is a non-integer value, for example. In cases in which a cycle count increment factor is used, normalization can occur to account for the increment factor.” CLOSING COMMENTS Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. a. STATUS OF CLAIMS IN THE APPLICATION a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a first action on the merits and are subject to a final rejection. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached on (571) 272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. September 25, 2026 /YAIMA RIGOL/ Primary Examiner, Art Unit 2135