Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 19/223,389 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
The instant application no. 19223389 filed 05/30/2025 Claims Priority from Provisional Application 63658342, filed 06/10/2024.
OBJECTIONS
Specification
The disclosure is objected to because of the following informalities: Applicant’s Specification does not clearly define the acronym PEC. Since it appears that PEC refers to program-erase cycle as recited in paragraph 0019, Applicant’s Specification should be corrected to clearly define the acronym in question.
Appropriate correction is required.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 10, 12 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 3, 5, 10, 12 and 18, the limitations “PEC(s)” render the claims indefinite since it is not clear what these limitations refer to and Applicant’s Specification does not expressly define the acronym PEC. It appears that PEC refers to program-erase cycle as recited in par. 0019; thus, the pending claims should be amended to define the acronym. Appropriate clarification/correction is required.
CLAIM CONSTRUCTION
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II).
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Note that the limitations “in response to” (in method claims 9, 13-14) may never be reached within the scope of the claim under the broadest reasonable interpretation since the condition to which the “in response to” statement is subject may never occur within the scope of the claim. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II).
It is suggested method claims 9 and 13-14 be amended to first require the condition to which the “in response to” statement is subject to occur and then in response to the condition occurring, performing the rest of the limitations. For example, claim 9 should be amended to read “determining an erase operation is being performed on the block; updating, in response to the erase operation being performed on the block,…”.
Additionally, note that apparatus claims 16 and 19-20 have been written as a hybrid claims which recite both a non-transitory computer readable storage medium in the preamble and method steps “within the body of the claim that also contain contingent limitations. It is suggested claims 16 and 19-20 be amended in the same manner as claim 9.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220398040 A1) in view of Neufeld et al. (US 20200004671).
1. A system, comprising: a memory device; and [Kang teaches memory device 100 (fig. 1 and related text)]
a processing device operatively coupled to the memory device, the processing device to perform operations, comprising: performing a program operation on a block of the memory device; [Kang teaches “[0049] For example, the operation controller 210 may control the memory device 100 to perform the write operation on the selected memory block among the plurality of memory blocks according to a write request received from the host 300.”]
retrieving, from a metadata structure associated with a block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device; [Kang teaches “[0094] Referring to FIG. 4, the memory block may include the main area storing user data and the spare area storing meta information. The meta information may be information for managing the user data and may include mapping information, erase and write count information, read count information, the lifetime information…” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.”], thus, using erase count as well as type information; where count information and lifetime information (which includes maximum erase counts for different block types) and thus reflects a type of the block are retrieved from the meta information are or metadata structure of the memory block
determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and [Kang teaches “[0052] The lifetime information controller 220 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block (thus including both erase count and write operation count to determine lifetime information).” “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text)]
updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function.
[0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value.
[0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.”
“ The operation controller 210 may control the memory device 100 to store write data corresponding to the write request and the lifetime information including the lifetime level of the selected memory block in the selected memory block. The memory device 100 may store the write data in a main area of the selected memory block and store the lifetime information in a spare area.” (par. 0049) “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” “[0107] In FIG. 6, the lifetime level of the memory block may be determined to be between 1 and N, where N is a natural number greater than or equal to 2, N representing the greatest lifetime level, which is predetermined. The alert level may be K, where K is a natural number greater than 1 and less than or equal to N. When the lifetime level of the memory block is greater than or equal to the alert level, the storage device may provide the flag indicating that the lifetime of the memory block is in the alert state to the host.” “[0111] The lifetime level of the memory block may determine a lifetime level corresponding to a section to which the erase and write count of the memory block belongs among the plurality of sections included in the lifetime level table. In an embodiment, the largest reference value Ref_N−1 among the plurality of reference values Ref_1 to Ref_N−1 may be the maximum erase and write count of the memory block.” (figs. 6 and 7 and related text)] where the alert level for the block determined according to lifetime level of the memory block determined according to the remaining program erase cycles for the memory block is updated and represents a media endurance metric value; however, Kang does not expressly refer to the wear ratio or lifetime level of the memory block used to update an endurance metric value; however, regarding these limitations, Neufeld teaches [“[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.” “[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.” Thus, using the wear ratio or rate of P/E cycles for the different memory types to update an expected EOL, which corresponds to the media endurance metric value for each of the memory types].
Kang and Neufeld are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of Kang to explicitly use the lifetime level or wear ratio which includes the number of P/E cycles for the different types of memory blocks to calculate an end of life estimate or media endurance metric for each of the memory types as taught by Neufeld since doing so would provide the benefits of [“ In some embodiments, as the memory device continues in operation, the controller and/or host can monitor usage to determine whether to reconfigure the memory device to change the amount of memory assigned to the high endurance section. For example, if the usage patterns suggest more high endurance memory is needed, some of the MLC memory section could be switched to SLC operation and added to the high endurance memory section.” (par. 0054) thus optimizing the memory’s lifetime (par. 0002)].
Therefore, it would have been obvious to combine Kang and Neufeld for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The system of claim 1, wherein the operations further comprise: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [Kang teaches “[0052] The lifetime information controller 220 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block (thus including both erase count and write operation count to determine lifetime information).” “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block into a lifetime level function including a maximum erase and write count of the memory block.” Kang teaches “[0094] Referring to FIG. 4, the memory block may include the main area storing user data and the spare area storing meta information. The meta information may be information for managing the user data and may include mapping information, erase and write count information, read count information, the lifetime information…” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text). Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.” “[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.”].
3. The system of claim 1, wherein the wear ratio represents a relationship between a first number of PECs of a first erase-program scheme that causes a first amount of cell damage to a block and a second number of PECs of a second erase-program scheme that causes a second amount of cell damage to a block, wherein a difference between the first amount of cell damage and the second amount of cell damage is less than a predefined threshold [Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.
[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.
[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711…” (thus, the difference between the wear or damage of the first type of memory and second type of memory may be found to be less than a threshold)].
4. The system of claim 1, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the operations further comprise: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711… [0061] Returning to FIG. 8, at step 711 the host is alerted to the EOL imbalance. If either the SLC section 613 or the MLC section 611 is aging relatively rapidly, the host may decide to reconfigure the memory. Continuing with the above example, the high endurance SLC section 613 is being heavily written and the host may decide to transfer some of the MLC section 611 to the high endurance SLC section 613, subsequently operating memory cells of the transferred portion in SLC mode. The host may also have additional information, such as information indicating that high usage rate of the high endurance section 613 is temporary and decide not to reconfigure at this time. If the host decides to reconfigure the memory at step 713, the host's reply to the memory system requests such a reconfiguration, which is executed at step 715 before looping back to step 705. If the memory is not to be reconfigured, the flow loops back from step 713 to step 705 for continued operation without reconfiguring the memory… [0080] At step 921, the relative wear levels of the sections are checked to see whether one of these areas is approaching its End Of Life (EOL) more rapidly than another. For example, even though the SLC section 813 has a higher endurance level than the MLC section 811, it may still be undergoing very intense write rates, so that it is nearing its EOL while the MLC section 811 is still relatively fresh. If the different memory sections are aging in a relatively balanced manner, such as the variation in their EOL values varying less than some threshold (No path), the flow continues back to 909. If, instead an imbalance is found (Yes path), the controller 802 informs the host 820 at step 923. The controller 802 receives the reply from host 820 at step 925 and, if a reconfiguration is requested, the controller 802 reconfigures the memory device 804 at step 927, transferring some of the memory cells of MLC section 811 to SLC section 813, or from SLC section 813 to MLC section 811, as requested by the host. After step 927 the flow then loops back to 909.”].
5. The system of claim 1, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first PEC [Kang teaches “[0053] For example, the lifetime information controller 220 may determine the lifetime level based on a section to which the erase and write count of the selected memory block belongs among a plurality of sections included in the lifetime level table. The lifetime level table may include a plurality of lifetime levels respectively corresponding to a plurality of sections divided by a plurality of reference values. As another example, the lifetime information controller 220 may determine the lifetime level by putting the erase and write count of the selected memory block (where erase and write counts correspond to a first PEC) into a lifetime level function including a maximum erase and write count of the memory block.” “[0104] Referring to FIG. 6, the lifetime level function may include a maximum erase and write count of the memory block. The maximum erase and write count of the memory block may vary according to a type of the memory block. For example, in a case of the SLC and the MLC, the maximum erase and write count may be differently set.” (which corresponds to also including a block type in calculating the lifetime level or wear ratio of the memory block) “[0105] When putting the erase and write count of the memory block into the lifetime level function, the lifetime level of the memory block may be determined.” Where the lifetime function also includes EW count of block shown as X (figs. 6 and 7 and related text). Neufeld teaches “[0058] FIG. 9 is a flowchart expanding out step 709 of FIG. 8 in one embodiment. At step 731 the memory system monitors an aging factor, in this embodiment the rate of program/erase cycles, for the high density memory section 611. For example, this can be monitored by MML 158 on the controller 102. Based on this rate, an estimated End of Life (EOL) value can be determined at step 733. For example, if the high density memory section 611 has a capacity of 3 GB, has an expected remaining endurance of 5,000 P/E cycles, and is being written at 3 GB per day, the expected EOL is 5,000 days.[0059] At step 735, the memory monitors the rate of P/E cycles (or other aging factor) for the high endurance memory section 613, estimating an expected EOL for the high endurance memory section 613 at step 737. For example, if the high endurance memory section 613 has a capacity of 2 GB, has an expected remaining endurance of 50,000 P/E cycles, and is being written at the rate of 100 GB per day, the expected EOL is 1,000 days for the high endurance memory section 613.”].
7. The system of claim 1, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [Kang teaches “Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function. [0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value. [0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.” Where indicating alert to the host continues to use the memory block. Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705 (where on looping back, the block continues to be allocated for use). If the difference is above the threshold, the imbalance is reported out to the host at step 711.”].
8. A method, comprising: performing, by a processing device, a program operation on a block of a memory device; retrieving, from a metadata structure associated with the block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device; determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [The rationale in the rejection of claim 1 is herein incorporated].
9. The method of claim 8, further comprising: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [The rationale in the rejection of claim 2 is herein incorporated].
10. The method of claim 8, wherein the wear ratio represents a relationship between a first number of PECs of a first erase-program scheme that causes a first amount of cell damage to a block and a second number of PECs of a second erase-program scheme that causes a second amount of cell damage to a block, wherein a difference between the first amount of cell damage and the second amount of cell damage is less than a predefined threshold [The rationale in the rejection of claim 3 is herein incorporated].
11. The method of claim 8, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the method further comprises: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [The rationale in the rejection of claim 4 is herein incorporated].
12. The method of claim 8, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first PEC [The rationale in the rejection of claim 5 is herein incorporated].
14. The method of claim 8, further comprising: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [The rationale in the rejection of claim 7 is herein incorporated].
15. A non-transitory computer-readable storage medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising: performing a program operation on a block of a memory device; retrieving, from a metadata structure associated with the block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device; determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation; and updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device [The rationale in the rejection of claim 1 is herein incorporated].
16. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: updating, in response to an erase operation being performed on the block, the value reflecting the type and the corresponding number of erase operations performed on the block of the memory device [The rationale in the rejection of claim 2 is herein incorporated].
17. The non-transitory computer-readable storage medium of claim 15, wherein the memory device comprises a plurality of dynamically reconfigurable blocks, and wherein the operations further comprise: reconfiguring, based on data storage requirements of a host system, at least a portion of the plurality of dynamically reconfigurable blocks [The rationale in the rejection of claim 4 is herein incorporated].
18. The non-transitory computer-readable storage medium of claim 15, wherein the type and the corresponding number of erase operations performed on the block comprise erase operations performed on the block during a first PEC [The rationale in the rejection of claim 5 is herein incorporated].
20. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and allocating, in response to determining that the media endurance metric value of the block does not satisfy the threshold criterion, the block for continued use in the memory device [The rationale in the rejection of claim 7 is herein incorporated].
Claims 6, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220398040 A1) in view of Neufeld et al. (US 20200004671) as applied in the rejection of claims 1, 8 and 15 above, and further in view of Barndt et al. (US 10282111).
6. The system of claim 1, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and [Kang teaches “Kang teaches “[0044] The memory controller 200 may set the lifetime determination reference and an alert level based on a lifetime reference setting command received from the host 300. The lifetime determination reference may be a reference for determining the lifetime level of the memory block based on the erase and write count of the memory block. The alert level may be a threshold lifetime level at which it is determined that the lifetime of the memory block is in an alert state. In an embodiment, the lifetime determination reference may include at least one of a lifetime level table and a lifetime level function.
[0045] When the memory controller 200 does not receive the lifetime reference setting command from the host 300, the memory controller 200 may set the lifetime determination reference and the alert level as a preset default value.
[0046] The memory controller 200 may determine the lifetime level of the selected memory block based on the lifetime determination reference and the erase and write count of the selected memory block. When the lifetime level of the selected memory block is greater than or equal to the alert level, the memory controller 200 may provide lifetime information including the lifetime level of the selected memory block and a flag indicating that the lifetime of the selected memory block is in an alert state to the host 300.” Neufeld teaches “[0060] At step 739, the EOLs of the two sections are compared. For the example given above, the EOL of the high density memory section 611 is 5 times the EOL of the high endurance memory section 613. If this difference in EOL values is above some threshold level, say a ratio of 2:1 or other value in either direction, an imbalance is determined at step 741. If the difference is below the threshold, flow loops back to step 705. If the difference is above the threshold, the imbalance is reported out to the host at step 711.”] but the combination does not expressly disclose retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device; however, regarding these limitations, Barndt teaches [“ The expected remaining number of cycles for a given block may be determined by subtracting the current cycle count for the block from the expected cycle count for the block. The subject system determines when the expected remaining number of cycles in a block of a given set of blocks is falling behind the expected remaining number of cycles of other blocks of the given set of blocks. In this instance, the subject system marks the block as temporarily inactive which prevents the block from being utilized in the data storage operations…” (col. 4, lines 8-26) “ The blocks 202A-P may each be associated with a status that may be, for example, stored by the controller 114 in the RAM 122. The status of the blocks may include, for example, active blocks, retired blocks, manufacturer bad blocks (MBBs), grown bad blocks (GBBs), or temporarily inactive blocks, which may also be referred to as on vacation blocks (OVBs). Blocks that are active may be available for data storage operations (e.g. reading/writing); however, blocks that are retired, MBBs, GBBs, or temporarily inactive may not be available for data storage operations. In FIG. 2, the blocks 202B,G,H,N that are shaded are blocks that are temporarily inactive and therefore are not available for data storage operations.” (col. 7, line 63-col.8, line 8) “Prior to performing any data storage operations on the flash memory circuits 112A-N, the controller 114 selects the first flash memory circuit 112A of the flash memory device 110 (402). The controller 114 performs rapid program/erase (P/E) cycles on one block 202A from the first flash memory circuit 112A until a quality metric associated with the block 202A falls below a minimum quality level (404). The quality metric may be, for example, RBER, error count, program time, etc. The controller 114 then marks the block 202A as inactive, or retired, such that the block 202A will not be available for data storage operations (406).” (col. 10, lines 14-24)].
Kang, Neufeld and Barndt are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of the combination to include in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device as taught by Barndt since doing so would provide the benefits of [extending the life of the memory and allowing for evening the wear of memory blocks].
Therefore, it would have been obvious to combine Kang and Neufeld with Barndt for the benefit of creating a storage system/method to obtain the invention as specified in claim 6.
13. The method of claim 8, further comprising: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device [The rationale in the rejection of claim 6 is herein incorporated].
19. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: determining whether the media endurance metric value of the block of the memory device satisfies a threshold criterion based on a threshold value; and retiring, in response to determining that the media endurance metric value of the block satisfies the threshold criterion, the block from use in the memory device [The rationale in the rejection of claim 6 is herein incorporated].
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Dancho et al. (US 9442662) teaches “In some embodiments, after a second predefined condition occurs (620), the storage controller obtains (622), for each of the plurality of die, an updated endurance metric. In some embodiments, storage controller 120 or a component thereof (e.g., endurance metric module 214, FIG. 2A) is configured to store an updated endurance metric for each of the plurality of die. In some embodiments, the updated endurance metric is based on the average bit error rate for the one or more blocks of each die, which was stored in response to detecting the first predefined condition. In some embodiments, the updated endurance metric is based on an erase time associated with the die or the amount of time required to successfully decode a codeword stored in the die. In some embodiments, the updated endurance metric for a respective die is stored in endurance metric field 242 of characterization vector 236 associated with the respective die and replaces the previous value stored in endurance metric field 242. In some embodiments, the second predefined condition is a periodic trigger (e.g., every Y days, every M PE cycles performed on the respective die, etc.).” (col. 12, line 66-col. 13, line 18). “In some embodiments, after a predefined condition occurs, the storage controller obtains, for each of the plurality of die, an updated endurance metric. In some embodiments, storage controller 120 or a component thereof (e.g., endurance metric module 214, FIG. 2A) is configured to store an updated endurance metric for each of the plurality of die. In some embodiments, the updated endurance metric for a respective die is stored in endurance metric field 242 of characterization vector 236 associated with the respective die and replaces the previous value stored in endurance metric field 242. In some embodiments, the second predefined condition is a periodic trigger (e.g., every Y days, every M PE cycles performed on the respective die, etc.)… In some embodiments, after the predefined condition occurs, the storage controller re-sorts the plurality of die into a plurality of updated die groups based on their corresponding updated endurance metrics, where each updated die group includes one or more die and each updated die group is associated with a range of endurance metrics.” (col. 15, lines 6-31).
Chen et al. (US 20130173844) teaches “ One indicator is program/erase (P/E) cycles. Typically, a block in the SLC portion or the MLC portion is erased and then programmed by writing data into the cells of the block. Each time a block undergoes a P/E cycle, a counter may be incremented. The number of the counter may thus provide one indicator of the age of the block.” (par. 0036) P/E cycles may be monitored for each of the blocks in the SLC portion and the MLC portion (par. 0036) “[0064] In one embodiment, the data construct may include data so that the `wear balancing` (discussed in more detail below) attempts to make the wear for the SLC portion balanced with the MLC portion. For example, the data construct indicating the preferred ratio of wear between the SLC portion and the MLC portion may be a predetermined constant value… For example, the data construct may comprise a curve or a piece-wise linear function, which may comprise more of optimal wear driving. The curve may account for a memory device that begins with a large pool of blocks and ends with a small pool of blocks. In particular, the number of MLC spare blocks typically gets smaller as the devices ages, thereby increasing the MLC portion stress. So that, the optimal curve may comprise overstressing the SLC portion at the beginning of life of the memory device (which may also provide better performance) more than required to balance the wear of the current SLC versus MLC ratio. In this way, during the earlier operation of the memory device, the MLC portion operates at lower stress and has an extra margin for operation. As the memory device proceeds toward its end-of-life (EOL), when the MLC portion write amplification increases, the wear in both the SLC portion and the MLC portion will converge near EOL point.”
Kankani et al. (US 20160342344 ) teaches “[0107] FIG. 4 is a block diagram illustrating a data structure (e.g., an endurance estimation table 226) for storing endurance estimates for different encoding formats based on various status metrics (or various values of a single status metric) associated with a particular NVM portion of a storage device, in accordance with some embodiments. In some embodiments, a particular endurance estimation table 226 is used to store endurance estimates for different encoding formats (e.g., SLC, MLC, and TLC) based on various values of a first status metric (e.g., a consistently-measured bit error rate of the lower page of a flash memory cell) and one or more other endurance estimation tables 226 are used to store endurance estimates for different encoding formats (e.g., SLC, MLC, and TLC) based on various values for one or more other status metrics that are distinct from the first status metric (e.g., retry rate, P/E cycles, number of total bytes written, or a combined status metric). Therefore, a particular memory device of a storage device (e.g., storage medium 132, FIG. 1, or a portion thereof, such as a first die of the storage medium 132), in some embodiments, is associated with one or more endurance estimation tables depending on the number and type of status metrics used to monitor the health of NVM portions within the particular memory device. As one example, if the particular memory device uses BER as the status metric to monitor health of a first die and uses P/E cycles to monitor health of a second die, then the particular memory device would be associated with two endurance estimation tables (a first endurance estimation table that provides endurance estimates for various BER values and a second endurance estimation table that provides endurance estimates for various values of P/E cycles remaining).”
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
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June 4, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
Prosecution Insights