DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 25-27, 34, and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi et al. (US Pub. No. 2018/0074757), hereinafter referred to as Yamaguchi, in view of Chen et al. (US Pub. No. 2014/0006681), hereinafter referred to as Chen.
Referring to claims 21 and 34, Yamaguchi discloses method, comprising: accessing a non-volatile memory express (NVMe) command and a physical region page (PRP) entry from a memory of a virtual machine (VM) (fig. 3, Host Memory side NVMe Command and PRP entries; a single root I/O virtualization (SRIOV) standard is used. SRIOV is a technique that creates a plurality of new devices based on, for example, one PCIe/NVMe device (one physical resource) and allocates a plurality of virtual machines to the new devices, [0016]; host 300 prepares a command and a PRP and stores the command and the PRP in the DRAM 36 which is a host memory. Then, the host 300 updates the doorbell in the NVMe registers 54. Then, the CPU 12 of the PCIe switch 10A fetches the SQ entry and the PRP in the DRAM 36 (ST1 to ST3), [0067]); generating a backend NVMe command and a backend PRP entry based on the VM PRP entry (PCIe switch 10A reconstructs the fetched command as a command #1 and a command #2. In addition, the PCIe switch 10A reconstructs the fetched PRP as a PRP #1 and a PRP #2 (S6), [0081]); and
storing the backend NVMe command and the backend PRP entry in a backend memory device separate from the host memory device, thereby causing a solid-state drive (SSD) device (in the case of the command to be transmitted to the SSD 21A-0, the CPU 12 updates the doorbell of the SSD 21A-0, [0069]) to: access the backend NVMe command and the backend PRP entry from the backend memory device (The command #1 is an NVMe command to be transmitted to the device #1 and the command #2 is an NVMe command to be transmitted to the device #2. The PRP #1 is a PRP list to be transmitted to the device #1 and the PRP #2 is a PRP list to be transmitted to the device #2. The commands #1 and #2 and the PRPs #1 and #2 are stored in the local memory 13, [0081]); and access, based on the backend NVMe command and the backend PRP, a data buffer of the host memory device (DRAM 36 stores, for example, a submission queue (SQ)…In the SQ entry, an NVMe command which is transmitted from the host 300 to the PCIe switch 10A is stored in a queue (circular buffer), [0031-0032]).
While Yamaguchi discloses the PRP entry in a host memory device (the PRP in the DRAM 36 which is a host memory, [0067]), generating the backend PRP entry (PCIe switch 10A reconstructs the fetched command as a command #1 and a command #2. In addition, the PCIe switch 10A reconstructs the fetched PRP as a PRP #1 and a PRP #2 (S6), [0081]), and a data buffer of the host memory device (DRAM 36 stores, for example, a submission queue (SQ)…In the SQ entry, an NVMe command which is transmitted from the host 300 to the PCIe switch 10A is stored in a queue (circular buffer), [0031-0032]), Yamaguchi does not appear to explicitly disclose translating a guest physical address (GPA) from the VM memory to a corresponding host physical address (HPA) in a host memory device that hosts the VM memory; the entry to comprising the corresponding HPA; and the data buffer accessed according to the corresponding HPA.
However, Chen discloses translating a guest physical address (GPA) from the VM memory to a corresponding host physical address (HPA) in a host memory device that hosts the VM memory and the entry comprising the corresponding HPA, and the data buffer accessed according to the corresponding HPA (translation procedure is performed to access the GPA to HPA memory structure(s) 112 to translate the guest physical address 104 to the host physical address 106…a second TLB is accessed for the GPA to HPA translation; [0030-0031]).
Yamaguchi and Chen are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yamaguchi and Chen before him or her, to modify the storage system of Yamaguchi to include the virtual machine memory configuration of Chen in order to facilitate the sharing of memory resources.
The suggestion/motivation for doing so would have been to manage the sharing of physical memory resources (Chen: [0007-0008]).
Therefore, it would have been obvious to combine Yamaguchi and Chen to obtain the invention as specified in the instant claim.
As to claims 25 and 38, Yamaguchi discloses storing the backend NVMe command and the backend PRP entry further comprises ringing a doorbell of the SSD device to cause the SSD device to access the backend memory (fig. 3, Host Memory side NVMe Command and PRP entries; host 300 prepares a command and a PRP and stores the command and the PRP in the DRAM 36 which is a host memory. Then, the host 300 updates the doorbell in the NVMe registers 54. Then, the CPU 12 of the PCIe switch 10A fetches the SQ entry and the PRP in the DRAM 36 (ST1 to ST3), [0067]).
As to claims 26 and 39, Yamaguchi discloses the VM is one VM of a plurality of VMs (SRIOV is a technique that creates a plurality of new devices based on, for example, one PCIe/NVMe device (one physical resource) and allocates a plurality of virtual machines to the new devices, [0016]) that are each associated with a compute node of a plurality of compute nodes (the master SSD updates the doorbells of the other SSDs (the other nodes), [0114]); and the backend memory device is separate from a respective memory device of each of the plurality of compute nodes (The commands #1 and #2 and the PRPs #1 and #2 are stored in the local memory 13, [0081]).
As to claims 27 and 40, the combination of Yamaguchi in view of Chen discloses the GPA is within a guest physical address range and the HPA is in a host physical address range different from the guest physical address range (Chen: translation procedure is performed to access the GPA to HPA memory structure(s) 112 to translate the guest physical address 104 to the host physical address 106…a second TLB is accessed for the GPA to HPA translation; [0030-0031]). The suggestion/motivation to combine remains as indicated above.
Claims 22-24 and 35-37 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Chen, as applied to claims 21, 25-27, 34, and 38-40 above, further in view of Li et al. (US Pub. No. 2018/0088978), hereinafter referred to as Li.
As to claims 22 and 35, the combination of Yamaguchi in view of Chen does not appear to explicitly disclose translating the GPA to the HPA comprises: sending, by a local NVMe virtualization (LNV) device to an input-output memory management unit (IOMMU), an address translation request comprising the GPA; and receiving, from the IOMMU in response to the address translation request, the HPA.
However, Li discloses translating the GPA to the HPA comprises: sending, by a local NVMe virtualization (LNV) device to an input-output memory management unit (IOMMU), an address translation request comprising the GPA; and receiving, from the IOMMU in response to the address translation request, the HPA (integrated I/O 112 may facilitate I/O communications with I/O devices such as NVMe device 150 via link 140 (e.g., using PCIe or NVMe protocols) in support of VMs or containers 160-1 to 160-N…integrated I/O 112 may also include a direct memory access (DMA) engine 114 and an IOMMU 115…One such feature is a Lookup DMA remapping table 109 maintained at IOMMU 115 that may be utilized to translate guest physical addresses (GPAs) used by VMs or containers to host physical addresses (HPAs) used by DMA engine 114 to write or read data to/from host physical memory or storage 120, [0025-0026]).
Yamaguchi, Chen, and Li are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yamaguchi, Chen, and Li before him or her, to modify the storage system of Yamaguchi in view of Chen to include the translation architecture of Li because the architecture would facilitate efficient I/O access to host physical memory.
The suggestion/motivation for doing so would have been to provide efficient memory access (Li: [0026]).
Therefore, it would have been obvious to combine Yamaguchi, Chen, and Li to obtain the invention as specified in the instant claim.
As to claims 23 and 36, the combination of Yamaguchi, Chen, and Li discloses the backend memory stores the backend NVMe command and the PRP entry for the LNV device (Yamaguchi: The command #1 is an NVMe command to be transmitted to the device #1 and the command #2 is an NVMe command to be transmitted to the device #2. The PRP #1 is a PRP list to be transmitted to the device #1 and the PRP #2 is a PRP list to be transmitted to the device #2. The commands #1 and #2 and the PRPs #1 and #2 are stored in the local memory 13, [0081]; Li: I/O access using IOMMU and/or SR-IOV technologies may be facilitated via use of isolated virtual functions (VFs) at a memory or storage device such as an SSD, [0019]). The suggestion/motivation to combine remains as indicated above.
As to claims 24 and 37, the combination of Yamaguchi, Chen, and Li discloses presenting a virtual SSD device using the LNV device (Yamaguchi: SRIOV is a technique that creates a plurality of new devices based on, for example, one PCIe/NVMe device (one physical resource) and allocates a plurality of virtual machines to the new devices, [0016]; PCIe link 53 maps a virtual memory to physical memories of the SSDs, [0042]; Li: I/O access using IOMMU and/or SR-IOV technologies may be facilitated via use of isolated virtual functions (VFs) at a memory or storage device such as an SSD, [0019]). The suggestion/motivation to combine remains as indicated above.
Allowable Subject Matter
Claims 28-33 are allowed
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2018/0129616 of Liang et al. is pertinent to GPA and HPA translation in a NVMe system. The US Pub. No. 2021/0200703 of Simionescu et al. is pertinent to a virtual NVMe environment and address translation.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
The applicant should use this period for response to thoroughly and very closely proof read and review the whole of the application for correct correlation between reference numerals in the textual portion of the Specification and Drawings along with any minor spelling errors, general typographical errors, accuracy, assurance of proper use for Trademarks ™, and other legal symbols ®, where required, an Abstract on a clean page (i.e., no Titles, Attorney information, line numbers, page numbers, exc... (37 CFR 1.72(b)) just a heading “ABSTRACT” and a paragraph less than 150 words), and clarity of meaning in the Specification, Drawings, and specifically the claims (i.e., provide proper antecedent basis for “the” and “said” within each claim) with each claim increasing in numerical order and ending in a period {if amended}. Minor typographical errors could render a Patent unenforceable and so the applicant is strongly encouraged to aid in this endeavor.
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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