DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The “mean for” limitations of Claims 19-20 are interpreted in view of the description of the features in paragraphs [0072], [0074], [0076], and [0079-0080] of the Applicant’s specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-9, 11, 13-14, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Narayanappa et al. (US Pub No. 2023/0385210), hereinafter referred to as Narayanappa.
Referring to claim 1, Narayanappa discloses a data storage device, comprising: a connector configured to couple the data storage device to a host with first and second full-duplex communication lanes and a half-duplex communication lane (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode); a first data storage controller coupled to a first memory of the data storage device and coupled to both the first and second full-duplex communication lanes of the connector; and a second data storage controller coupled to a second memory of the data storage device and coupled to the half-duplex communication lane of the connector (a plurality of storage controllers 202, each of which controls a respective data storage device 204, [0050]; NOTE: as the storage controllers are connected to the host by the anticipated USB Type-C receptacles and cable, the storage controllers are “coupled to” the full and half duplex communication lanes available from the USB Type-C receptacle and cabling standard).
As to claim 4, Narayanappa discloses the connector comprises a Universal Serial Bus Type-C (USB-C) connector; the first full-duplex communication lane comprises a first Tx/Rx lane of the USB-C connector; the second full-duplex communication lane comprises a second Tx/Rx lane of the USB-C connector; and the half-duplex communication lane comprises a D-/D- lane of the USB-C connector (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode).
As to claim 5, Narayanappa discloses the first data storage controller is configured to transfer data to the host using USB 3.2 Gen 2x2 or higher using the first and second Tx/Rx lanes of the USB-C connector (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode; therefore, the disclosed USB 3.2 Gen2x2 with Type C Interface indicates that anticipated storage controllers are “configured to transfer data to the host using” the anticipated capabilities).
AS to claim 6, Narayanappa discloses the first data storage controller is configured to transfer data to the host at 10 giga- bits-per-second (Gbps) or higher using the first Tx/Rx lane of the USB-C connector and at 10 Gbps or higher using the second Tx/Rx lane of the USB-C connector; and the second data storage controller is configured to transfer data to the host at 480 mega-bits-per-second (Mbps) using the D+/D- lane of the USB-C connector (NOTE: the host to storage controller configuration is anticipated as USB 3.2 Gen2x2 with Type C Interface which provides two separate 10 Gbps lanes, lane 1 and lane 2 to provide 10 Gbps for a combined 20 Gbps by running both lanes in parallel over the USB-C connector, and further supports the single-lane modes USB Gen 2 2X1 which is 1 lane at 10Gbps or 1x2 which is 2 lanes at 5Gbps totaling 10 Gbps; the anticipated USB generation supports legacy USB 2.0 data lines (D+/D-) which provides a 480 Mbps transfer rate. Therefore, the storage controllers are anticipated to be “configured to transfer data to the host at” the supported transfer rates).
As to claim 7, Narayanappa discloses the USB-C connector of the data storage device is a USB-C socket configured to mate with a USB-C plug (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]).
As to claim 8, Narayanappa discloses the USB-C connector of the data storage device is a USB-C plug configured to mate with a USB-C socket (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]).
As to claim 9, Narayanappa discloses the first memory comprises a first plurality of NAND chips or dynamic random access memory (DRAM) chips; and the second memory comprises a second plurality of NAND chips or DRAM chips (any suitable type of memory can be used...such as dynamic random access memory (“DRAM”)…flash memory devices may be configured in a NAND, [0078]).
Referring to claim 11, Narayanappa discloses a method for use by a data storage device that includes a connector (a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0061]), a first memory and a first data storage controller, and a second memory and a second data storage controller (a plurality of storage controllers 202, each of which controls a respective data storage device 204, [0050]), the method comprising: using the first data storage controller to couple the first memory to first and second full-duplex communication lanes of the connector; using the second data storage controller to couple the second memory to a half-duplex communication lane of the connector (NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode, and as the storage controllers are between the storage and the host, the storage controllers are used “to couple” the memories to the full and half duplex communication lanes available from the USB Type-C receptacle and cabling standard); transferring data, using the first data storage controller, between the first memory and a host using both the first and second full-duplex communication lanes of the connector; and transferring data, using the second data storage controller, between the second memory and the host using the half-duplex communication lane of the connector (when a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller, [0045]; When the host and the data storage device both implement a USB Type C Receptacle…orientation detection and lane configuration happen, [0061]; NOTE: the anticipated USB Type-C provides the full and half duplex lanes for use in transferring data between the storage device and host through the respective storage controllers).
As to claim 13, Narayanappa discloses the transferring of data between the first memory and the host using both the first and second full-duplex communication lanes is performed in accordance with a first communication protocol; and the transferring of data between the second memory and the host using the half-duplex communication lane is performed in accordance with a second, different communication protocol (NOTE: the host to storage controller configuration is anticipated as USB 3.2 Gen2x2 with Type C Interface which provides two separate 10 Gbps lanes, lane 1 and lane 2 to provide 10 Gbps for a combined 20 Gbps by running both lanes in parallel over the USB-C connector, and further supports the single-lane modes USB Gen 2 2X1 which is 1 lane at 10Gbps or 1x2 which is 2 lanes at 5Gbps totaling 10 Gbps; the anticipated USB generation supports legacy USB 2.0 data lines (D+/D-) which provides a 480 Mbps transfer rate. Therefore, the anticipated USB 3.2 Gen2x2 support for legacy USB 2.0 teaches transferring data “in accordance with a second, different communication protocol” from the full-duplex protocol).
As to claim 14, Narayanappa discloses the first communication protocol is Universal Serial Bus (USB) 3.0 or higher, and the second communication protocol is USB 2.0 (USB 3.2 Gen2x2 with Type C Interface, [0060]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode).
As to claim 18, Narayanappa discloses transferring of data between the first memory and the host using the first full- duplex lane of the connector is performed at 10 giga-bits-per-second (Gbps) or higher; the transferring of data between the first memory and the host using the second full- duplex lane of the connector is performed concurrently at 10 Gbps or higher; and the transferring of data between the second memory and the host using the half- duplex lane of the connector is performed at 480 mega-bits-per-second (Mbps) (NOTE: the host to storage controller configuration is anticipated as USB 3.2 Gen2x2 with Type C Interface which provides two separate 10 Gbps lanes, lane 1 and lane 2 to provide 10 Gbps for a combined 20 Gbps by running both lanes in parallel over the USB-C connector, and further supports the single-lane modes USB Gen 2 2X1 which is 1 lane at 10Gbps or 1x2 which is 2 lanes at 5Gbps totaling 10 Gbps; the anticipated USB generation supports legacy USB 2.0 data lines (D+/D-) which provides a 480 Mbps transfer rate. Therefore, “transferring of data” according to the anticipated lane capabilities “is performed at” the supported transfer rates).
Referring to claim 19, Narayanappa discloses an apparatus (fig. 1C) comprising: means within a first data storage controller for coupling a first memory (a plurality of storage controllers 202, each of which controls a respective data storage device 204, [0050]) to first and second full-duplex communication lanes of a connector (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode); means within a second data storage controller for coupling a second memory (a plurality of storage controllers 202, each of which controls a respective data storage device 204, [0050]) to a half- duplex communication lane of the connector (USB 3.2 Gen2x2 with Type C Interface…the host and the data storage device both implement a USB Type C Receptacle, a USB Type-C-plug-to-Type-C-plug cable is required to connect the host and the data storage device, [0060-0061]; NOTE: as the storage controllers are connected to the host by the anticipated USB Type-C receptacles and cable, there are means “for coupling” the memory to the full and half duplex communication lanes available from the USB Type-C receptacle and cabling standard); means within the first data storage controller for transferring data between the first memory and a host using both the first and second full-duplex communication lanes of the connector; and means within the second data storage controller for transferring data between the second memory and the host using the half-duplex communication lanes of the connector (when a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller, [0045]; When the host and the data storage device both implement a USB Type C Receptacle…orientation detection and lane configuration happen, [0061]; NOTE: the anticipated USB Type-C provides the full and half duplex lanes means for transferring data between the storage device and host through the respective storage controllers).
As to claim 20, Narayanappa discloses the connector is a Universal Serial Bus-C (USB-C) connector; the means for transferring data between the first memory and the host using both the first and second full-duplex lanes comprises means for transferring data using USB 3.0 or higher; and the means for transferring data between the second memory and the host using the half-duplex lane comprises means for transferring data using USB 2.0 (USB 3.2 Gen2x2 with Type C Interface, [0060]; NOTE: the anticipated USB Type C generation features four SS differential pairs that operate as separate full-duplex channels for SS USB, Thunderbolt, and DP Alternate mode, and the legacy USB 2.0 data lines (D+/D-) operate in half-duplex mode).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Narayanappa in view of Nakazono et al. (US Patent No. 6880131), hereinafter referred to as Nakazono.
Regarding claim 10, as demonstrated above, Narayanappa teaches a host communicatively coupled to the data storage device, the first memory of the data storage device, and the second memory of the data storage device, and while Narayanappa discloses the host is configured to display to a user (host…tablet, [0049]; NOTE: at least the disclosed tablet host configuration implies a user display), Narayanappa does not appear to explicitly disclose displaying a first external drive and a second external drive.
However, Nakazono discloses displaying a first external drive and a second external drive (displays on the screen 23 various device names DEVICE of the various operative storage media such as a hard disk HDD, flexible disks FD1 and FD2, and so forth of the external storage device 40; col. 8, lines 1-5).
Narayanappa and Nakazono are analogous art because they are from the same field of endeavor, managing storage devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Narayanappa and Nakazono before him or her, to modify the storage system of Narayanappa to include the drive directory of Nakazono because the directory would provide the user with a visual representation of the storage components.
The suggestion/motivation for doing so would have been to allow the user to easily and visually recognize and manipulate the connected storage components (Nakazono: col. 2, lines 20-30).
Therefore, it would have been obvious to combine Narayanappa and Nakazono to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 2-3, 12, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2017/0161226 of Gerber et al. teaches a USB lane configuration supporting different communication protocols. The US Pub. No. 2009/0300259 of Lou et al teaches a multi-channel host connection in communication with a plurality of flash processing units in control of flash storage device.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
The applicant should use this period for response to thoroughly and very closely proof read and review the whole of the application for correct correlation between reference numerals in the textual portion of the Specification and Drawings along with any minor spelling errors, general typographical errors, accuracy, assurance of proper use for Trademarks ™, and other legal symbols ®, where required, an Abstract on a clean page (i.e., no Titles, Attorney information, line numbers, page numbers, exc... (37 CFR 1.72(b)) just a heading “ABSTRACT” and a paragraph less than 150 words), and clarity of meaning in the Specification, Drawings, and specifically the claims (i.e., provide proper antecedent basis for “the” and “said” within each claim) with each claim increasing in numerical order and ending in a period {if amended}. Minor typographical errors could render a Patent unenforceable and so the applicant is strongly encouraged to aid in this endeavor.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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