DETAILED ACTION
1. This Office Action is taken in response to Applicants’ application 19/224,026 filed on 5/30/2025.
Claims 1-20 are pending for consideration.
2. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Paul et al. (US Patent Application Publication 2022/0004488, hereinafter Paul), and in view of Park (US Patent Application Publication 2024/0086313).
As to claim 1, Paul teaches Amended) A data processing system [as shown in figures 1-4], comprising:
a first computing cluster, comprising a first computing device [compute brick 1, figure 1, 102; figure 3, node 1];
a second computing cluster, comprising a second computing device [compute brick 2, figure 1, 104; figure 3, node 2]; and
a connection device [for example, Memory Pooling Circuitry 1 (MPC), figure 3, 205-1], wherein the connection device is connected to the first computing device [as shown in figure 3], and is configured to manage (a memory address information of the first computing cluster that is provided by the first computing device and (b memory address information of the second computing cluster that is provided by the second computing device [The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs (abstract); ... Individual ones of the MPCs may include a decoder having a register, such as a translation lookaside buffer (TLB). Being able to program the register (such as a register within SMC 215 of FIG. 2) to dynamically allocate/de-allocate ranges of memory addresses (i.e. memory regions) of the shared memory among multiple CPUs to achieve a high level of performance in the overall DMA, such as a data center. “Dynamic allocation/deallocation,” or “dynamic programming” as used herein means an allocation/deallocation, or programming, which can change, for example as a function of time and/or as a function of changing parameters (¶ 0027); Programming each of the one or more MPCs may include programming a register of the one or more MPCs. Programming the register may include programming register entries 403-0 or 403-1 (the entries including information to translate DPAs to LMAs) such that the LMA translations result in respective LMAs to be processed by one or more memory controllers (MCs) coupled to the register based on non-contiguous MC memory regions 404-0 or 404-1 in each of the one or more MCs address spaces (representing memory space of the one or more MCs), the address regions having a predetermined granularity chosen by the programming agent ... (¶ 0043)]:
wherein the first computing device [the primary node -- The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs) ... (abstract); ... In SoC 300, four nodes 210, Node 1, Node 2, Node 3 and Node 4 (similar to those of FIG. 2), are communicatively coupled to four memory pooling circuitries (MPCs) 1-4, with one of the nodes, such as Node 1, serving as a primary node and the other nodes serving as secondary nodes as will be explained further below ... (¶ 0035)] is configured to:
receive an access request, wherein the access request is used to access memory space of the second computing device [as shown in figure 4, where node 1 receives the address of a access request and decodes the address; In operation, referring now to FIGS. 3 and 4, the primary Node 1 may execute a memory programming agent, such as a hypervisor, to perform a number of operations. In particular, the primary Node 1 may, prior to a memory transaction based on one or more requests from CPUs in any of Nodes 1-4, cause a programming of the HMM 402 (i.e. of memory addresses in the shared memory) and of one or more MPCs, such as respective MPCs of FIG. 3 (¶ 0041); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4 (¶ 0047)];
search the memory address information of the second computing cluster that is managed by the connection device for an address of the memory space [as shown in figure 4, where node 1 receives the address of a access request and decodes the address; In operation, referring now to FIGS. 3 and 4, the primary Node 1 may execute a memory programming agent, such as a hypervisor, to perform a number of operations. In particular, the primary Node 1 may, prior to a memory transaction based on one or more requests from CPUs in any of Nodes 1-4, cause a programming of the HMM 402 (i.e. of memory addresses in the shared memory) and of one or more MPCs, such as respective MPCs of FIG. 3 (¶ 0041); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4 (¶ 0047)]; and
access the memory space of the second computing device based on the address [The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs) ... (abstract); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4. After the programming stage, a memory transaction from one of the Nodes 1-4 in Soc 300 may be received by a MPC 205, and, if a register hit occurs at one of the Decoders 0 or 1, the HPAs for the memory transaction are translated into corresponding LMAs through DPAs, and sent to a corresponding MC of the MPC. A HMM, corresponding to a memory address map for the shared memory, may thus be implemented and controlled by programming, by a primary node, of one or more MPCs in a DMA ... Reference is now made to FIG. 5, which illustrates a flow 500 for the generation of LMA from HPA through DPA at a MPC, such as any of MPCs 205 of FIG. 3, according to some embodiments. Once a memory transaction request by a CPU of any of Nodes 1-4 is received at the MPC with a request for memory access, if the HPA address is successfully decoded, the MC translates the HPA to a DPA ... (¶ 0047-0050);
Park more expressively teaches this limitation -- Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus (abstract); When the second memory subsystem 220 determines that the data corresponding to the data read command exists in the second memory 230, the second memory subsystem 220 may share a transfer status of the memory data with the second processor 210 (S307), and may transmit an access permission message with respect to the corresponding data of the second memory 230 to the memory subsystem 120 (S308). In addition, the first memory subsystem 120 may compare data accessed through the second memory 230 and transfer the data to the first processor 110 (S309). Through this process, the first processor 110 may access the second memory 230 to read the corresponding data when the necessary corresponding data does not exist in the first memory 130 (¶ 0054-0055)].
Regarding claim 1, Paul teaches that the first computing device (i.e., the primary node) translates host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs) [The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs) ... (abstract); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4. After the programming stage, a memory transaction from one of the Nodes 1-4 in Soc 300 may be received by a MPC 205, and, if a register hit occurs at one of the Decoders 0 or 1, the HPAs for the memory transaction are translated into corresponding LMAs through DPAs, and sent to a corresponding MC of the MPC. A HMM, corresponding to a memory address map for the shared memory, may thus be implemented and controlled by programming, by a primary node, of one or more MPCs in a DMA ... Reference is now made to FIG. 5, which illustrates a flow 500 for the generation of LMA from HPA through DPA at a MPC, such as any of MPCs 205 of FIG. 3, according to some embodiments. Once a memory transaction request by a CPU of any of Nodes 1-4 is received at the MPC with a request for memory access, if the HPA address is successfully decoded, the MC translates the HPA to a DPA ... (¶ 0047-0050)], but does not expressively teach the first computing device accesses the memory space of the second computing device.
However, Park specifically teaches a first computing device accesses the memory space of the second computing device [Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus (abstract); When the second memory subsystem 220 determines that the data corresponding to the data read command exists in the second memory 230, the second memory subsystem 220 may share a transfer status of the memory data with the second processor 210 (S307), and may transmit an access permission message with respect to the corresponding data of the second memory 230 to the memory subsystem 120 (S308). In addition, the first memory subsystem 120 may compare data accessed through the second memory 230 and transfer the data to the first processor 110 (S309). Through this process, the first processor 110 may access the second memory 230 to read the corresponding data when the necessary corresponding data does not exist in the first memory 130 (¶ 0054-0055)].
Therefore, it would have been obvious for ones of ordinary skills in the art before the effective filing date of the claimed inventions to let a first computing device accesses the memory space of the second computing device, as specifically demonstrated by Park, and to incorporate it into the existing scheme disclosed by Paul, because Park teaches doing this allows each computing device of multiple computing device to mutually access each other’s memory and share data [The present disclosure also provides a bridge control method and system for a computing system that may configure heterogeneous convergence memory clusters capable of convergence and interoperation of memory networks by enabling mutual access to heterogeneous processors and memories connected to physically different chips (¶ 0011)].
As to claim 2, Paul in view of Park teaches The system according to claim 1, further comprising: a network device, configured to connect the first computing cluster to the second computing cluster [Paul – networking chip, figure 2, 220; Turning to FIG. 2, a simplified block diagram is shown illustrating an example pooled memory/disaggregated memory architecture (DMA) 200a including shared memory 205 capable of being accessed using load/store techniques by each of a plurality of independent nodes 210a-210n ... Thus, shared memory may be shared within a given DMA, or with other DMAs communicatively coupled to the given DMA via network connectivity, such as via networking chip 220 (¶ 0018)].
As to claim 3, Paul in view of Park teaches The system according to claim 1, wherein the connection device is connected to the first computing device by using a compute express link (CXL) protocol or a unified bus (UB) protocol [Paul -- The controller hub may be a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy and/or a Compute Express Link (CXL) interconnection hierarchy based on the CXL Specification. Examples of a controller hub include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH) (¶ 0017)].
As to claim 4, Paul in view of Park teaches The system according to claim 1, wherein: the first computing cluster further comprises a third computing device [Paul -- as shown in figure 3], and the connection device is configured to connect the first computing device to the third computing device [Paul -- as shown in figure 3]; and the first computing device is further configured to: obtain memory address information of the third computing device [Paul -- as shown in figure 4, where node 1 receives the address of a access request and decodes the address; In operation, referring now to FIGS. 3 and 4, the primary Node 1 may execute a memory programming agent, such as a hypervisor, to perform a number of operations. In particular, the primary Node 1 may, prior to a memory transaction based on one or more requests from CPUs in any of Nodes 1-4, cause a programming of the HMM 402 (i.e. of memory addresses in the shared memory) and of one or more MPCs, such as respective MPCs of FIG. 3 (¶ 0041); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4 (¶ 0047)]; perform addressing based on the memory address information of the third computing device and memory address information of the first computing device, to form the memory address information of the first computing cluster; and send the memory address information of the first computing cluster to the connection device [Paul -- The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs) ... (abstract); After the programming stage, the primary Node 1 may process parallel memory access requests to access non-contiguous host memory allocations in the HMM, the parallel memory access requests by workloads to be executed by one or more of the Nodes 0-4. After the programming stage, a memory transaction from one of the Nodes 1-4 in Soc 300 may be received by a MPC 205, and, if a register hit occurs at one of the Decoders 0 or 1, the HPAs for the memory transaction are translated into corresponding LMAs through DPAs, and sent to a corresponding MC of the MPC. A HMM, corresponding to a memory address map for the shared memory, may thus be implemented and controlled by programming, by a primary node, of one or more MPCs in a DMA ... Reference is now made to FIG. 5, which illustrates a flow 500 for the generation of LMA from HPA through DPA at a MPC, such as any of MPCs 205 of FIG. 3, according to some embodiments. Once a memory transaction request by a CPU of any of Nodes 1-4 is received at the MPC with a request for memory access, if the HPA address is successfully decoded, the MC translates the HPA to a DPA ... (¶ 0047-0050)].
As to claim 5, Paul in view of Park teaches The system according to claim 4, wherein: the memory address information of the first computing device comprises information about a plurality of memories of the first computing device; and the memory address information of the third computing device comprises information about a plurality of memories of the third computing device [Paul – multiple memory bricks and shared memory units as shown in figures 1, 2, 3 and 4; The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs (abstract)].
As to claim 6, Paul in view of Park teaches The system according to claim 1, wherein the first computing device is further configured to: after receiving the access request, determine that the access request is an access request used to access the memory space of the second computing device based on a determination that an address that the access request is used to access does not belong to a memory address of the first computing cluster [Park -- Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus (abstract); When the second memory subsystem 220 determines that the data corresponding to the data read command exists in the second memory 230, the second memory subsystem 220 may share a transfer status of the memory data with the second processor 210 (S307), and may transmit an access permission message with respect to the corresponding data of the second memory 230 to the memory subsystem 120 (S308). In addition, the first memory subsystem 120 may compare data accessed through the second memory 230 and transfer the data to the first processor 110 (S309). Through this process, the first processor 110 may access the second memory 230 to read the corresponding data when the necessary corresponding data does not exist in the first memory 130 (¶ 0054-0055)].
As to claim 7, Paul in view of Park teaches The system according to claim 1, wherein the connection device is further configured to: receive at least one of: the memory address information of the first computing cluster from the first computing device; or the memory address information of the second computing cluster from the second computing device [Paul -- The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs (abstract); ... Individual ones of the MPCs may include a decoder having a register, such as a translation lookaside buffer (TLB). Being able to program the register (such as a register within SMC 215 of FIG. 2) to dynamically allocate/de-allocate ranges of memory addresses (i.e. memory regions) of the shared memory among multiple CPUs to achieve a high level of performance in the overall DMA, such as a data center. “Dynamic allocation/deallocation,” or “dynamic programming” as used herein means an allocation/deallocation, or programming, which can change, for example as a function of time and/or as a function of changing parameters (¶ 0027); Programming each of the one or more MPCs may include programming a register of the one or more MPCs. Programming the register may include programming register entries 403-0 or 403-1 (the entries including information to translate DPAs to LMAs) such that the LMA translations result in respective LMAs to be processed by one or more memory controllers (MCs) coupled to the register based on non-contiguous MC memory regions 404-0 or 404-1 in each of the one or more MCs address spaces (representing memory space of the one or more MCs), the address regions having a predetermined granularity chosen by the programming agent ... (¶ 0043)].
As to claim 8, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 9, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 10, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 11, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 12, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 14, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
In addition, Paul in view of Park teaches a non-volatile memory [Paul -- Memory resources within memory bricks 108 and 110 may in general include any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100. Memory resources may be coupled to a controller hub through a memory interface (not shown). Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface (¶ 0016)].
As to claim 16, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 18, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 19, Paul in view of Park teaches The connection device according to claim 15, wherein the connection device is located external to the first computing cluster [Paul – as shown in figure 3, where the Memory Pooling Circuitry (MPC) is located outside of node 1].
As to claim 20, it recites substantially the same limitations as in claim 19, and is rejected for the same reasons set forth in the analysis of claim 19. Refer to “As to claim 19” presented earlier in this Office Action for details.
Conclusion
4. Claims 1-20 are rejected as explained above.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
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