DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Objections
Claims 2-8, 10-14 and 16-20 are objected to because of the following informalities:
Claim 2 should be amended to recite:
2. The data storage system of claim 1, wherein the adjusted voltage is an adjusted Vpassr, [[and]] the VB includes a plurality of virtual wordlines (VWLs), and the instructions, when executed by the at least one processor, further cause the at least one processor to[[:]] perform a read operation at least in part by: [[–]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted Vpassr to one or more remaining VWLs of the plurality of VWLs.
Claim 3 should be amended to recite:
3. The data storage system of claim 1, wherein the adjusted voltage is an adjusted BL bias voltage, [[and]] the VB includes a plurality of virtual wordlines (VWLs) and a plurality of bitlines (BLs), and the instructions, when executed by the at least one processor, further cause the at least one processor to[[:]] perform a read operation at least in part by: [[-]] applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted BL bias voltage to one or more of the plurality of BLs.
Claim 4 should be amended to recite:
4. The data storage system of claim 1, wherein the adjusted voltage is an adjusted SL voltage, [[and]] the VB includes a plurality of virtual wordlines (VWLs) and a plurality of physical blocks, and the instructions, when executed by the at least one processor, further cause the at least one processor to[[:]] perform a read operation at least in part by: [[-]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted SL voltage to one or more of the plurality of physical blocks.
Claim 5 should be amended to recite:
5. The data storage system of claim 1, wherein the VB includes a bit line (BL), the BL includes a string of cells electrically connected in series, and the adjusted voltage is to adjust a string current (Icell) of the string of cells.
Claim 6 should be amended to recite:
6. The data storage system of claim 5, wherein the determination of the cross-temperature condition includes determining that a read threshold voltage associated with the VB has increased above a default read threshold voltage, and the adjusted voltage is to increase the Icell.
Claim 7 should be amended to recite:
7. The data storage system of claim 5, wherein the determination of the cross-temperature condition includes determining that a read threshold voltage associated with the VB has decreased below a default read threshold voltage, and the adjusted voltage is to decrease the Icell.
Claim 8 should be amended to recite:
8. The data storage system of claim 1, wherein the VB includes a plurality of physical blocks, the measured program temperature includes an aggregation of program temperature values corresponding to respective ones of the plurality of physical blocks, and the measured read temperature includes an aggregation of read temperature values corresponding to respective ones of the plurality of physical blocks.
Claim 10 should be amended to recite:
10. The computer-implemented of claim 9, wherein the adjusted voltage is an adjusted Vpassr, [[and]] the VB includes a plurality of virtual wordlines (VWLs) and a plurality of bitlines (BLs), and the method further includes: [[–]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted Vpassr to one or more remaining VWLs of the plurality of VWLs.
Claim 11 should be amended to recite:
11. The computer-implemented of claim 9, wherein the adjusted voltage is an adjusted BL bias voltage, the VB includes a plurality of virtual wordlines (VWLs) and a plurality of bitlines (BLs), and the method further includes : [[-]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted BL bias voltage to one or more of the plurality of BLs.
Claim 12 should be amended to recite:
12. The computer-implemented of claim 9, wherein the adjusted voltage is an adjusted SL voltage, and the method further includes : [[-]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted SL voltage to one or more of the plurality of physical blocks.
Claim 13 should be amended to recite:
13. The computer-implemented of claim 9, wherein the VB includes a bit line (BL), the BL includes a string of cells electrically connected in series, and the adjusted voltage is to adjust a string current (Icell) of the string of cells.
Claim 14 should be amended to recite:
14. The computer-implemented of claim 9, wherein the VB includes a plurality of physical blocks, the measured program temperature includes an aggregation of program temperature values corresponding to respective ones of the plurality of physical blocks, and the measured read temperature includes an aggregation of read temperature values corresponding to respective ones of the plurality of physical blocks.
Claim 16 should be amended to recite:
16. The non-transitory computer readable media of claim 15, wherein the adjusted voltage is an adjusted Vpassr, [[and]] the VB includes a plurality of virtual wordlines (VWLs), and the instructions, when executed by the at least one processor, cause the at least one processor to[[:]] perform a read operation at least in part by: [[–]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted Vpassr to one or more remaining VWLs of the plurality of VWLs.
Claim 17 should be amended to recite:
17. The non-transitory computer readable media of claim 15, wherein the adjusted voltage is an adjusted BL bias voltage, [[and]] the VB includes a plurality of virtual wordlines (VWLs) and a plurality of bitlines (BLs), and the instructions, when executed by the at least one processor, further cause the at least one processor to[[:]] perform a read operation at least in part by: [[-]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted BL bias voltage to one or more of the plurality of BLs.
Claim 18 should be amended to recite:
18. The non-transitory computer readable media of claim 15, wherein the adjusted voltage is an adjusted SL voltage, [[and]] the VB includes a plurality of virtual wordlines (VWLs) and a plurality of physical blocks, and the instructions, when executed by the at least one processor, further cause the at least one processor to[[:]] perform a read operation at least in part by: [[-]]
applying a read voltage to a first VWL of the plurality of VWLs, and
applying the adjusted SL voltage to one or more of the plurality of physical blocks.
Claim 19 should be amended to recite:
19. The non-transitory computer readable media of claim 15, wherein the VB includes a bit line (BL), the BL includes a string of cells electrically connected in series, and the adjusted voltage is to adjust a string current (Icell) of the string of cells.
Claim 20 should be amended to recite:
20. The non-transitory computer readable media of claim 19, wherein the VB includes a plurality of physical blocks, the measured program temperature includes an aggregation of program temperature values corresponding to respective ones of the plurality of physical blocks, and the measured read temperature includes an aggregation of read temperature values corresponding to respective ones of the plurality of physical blocks.
Claims 6-7 and 20 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-9, 13-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2020/0411110 A1 (Getreuer) in view of US Patent Application Publication No. US 2010/0110793 A1 (Kim) in further view of US Patent Application Publication No. US 2016/0086675 A1 (Ray).
Regarding claim 1 and analogous claims 9 and 15:
Getreuer discloses, A data storage system (100) comprising: a memory device (104) including a virtual block (VB) (the memory device (103) includes a plurality of flash memory dies (144) including a plurality of blocks (152), which may be arranged into a plurality of garbage collection units (154), which include erasure blocks from across a plurality of dies (and therefore across a plurality of planes) (i.e., virtual block) [0052] [0056] [Figs. 2-3]); non-transitory computer readable media storing instructions thereon and at least one processor, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: (by disclosing firmware (i.e., stored in non-volatile memory) storing instructions for each of the processors (114) (116) (118) of the controller (112), which may also include the CTCM that operates to compensate for cross-temperature management control (200), and may be a firmware routine stored in a memory location and executed by one or more of the processors of the SSD controller (112) [0073]); measure a program temperature associated with the VB (by disclosing that the temperature at the time of programming (Tprogram) may be saved [0090]. Programming occurs to a GCU as a GCU is the unit of allocation [0056-0057]); measure a read temperature associated with the VB (the current temperature is also measured and obtained [0091], the current temperature is used as the temperature at the time of reading for a read operation (i.e., read temperature). The relevant granularity is a per GCU basis (i.e., a read temperature associated with the GCU) [0114-0118]); determine, based at least in part on the measured program temperature and the measured read temperature, a cross-temperature condition (by disclosing determining if the absolute value of the difference between the current temperature at the time of a read operation and the program temperature exceeds a difference threshold, which is considered a cross temperature condition [0116-0118]) and based on the determined cross-temperature condition, determine an adjusted voltage (by disclosing that a voltage shift increment is determined to be applied to the read voltage to determine an appropriate read voltage level [0118])
Getreuer does not explicitly disclose, but Kim teaches the adjusted voltage including one or more of: an adjusted pass through voltage (Vpassr) (by teaching that the read voltage applied to an unselected word line (i.e., pass through voltage – interpreted analogously with Applicant’s Specification, “Vpassr may be applied to unselected wordlines (WLs) of a block of a NAND flash device during a read operation) [Applicant’s Specification, [0030]) may be adjusted based on temperature [0010], which includes a difference in the temperature at programming and the current temperature when reading memory cells of a flash memory [0011-0012]. For example, when a read operation is performed at a higher temperature than programming, the threshold voltages may change, and therefore the voltages applied to the unselected wordlines should be change, according to the difference in programming temperature and the current temperature [0097-0100]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read operation performed after detecting a cross temperature condition as taught by Getreuer to include modifying the read voltages applied to the unselected wordlines according to the difference in temperatures between the time of programming and the time of reading as taught by Kim.
One of ordinary skill in the art would have been motivated to make this modification because it can compensate for the voltage shift experienced by the memory cells as a result of the shift in temperatures as taught by Kim in [0097-0100].
Getreuer in view of Kim do not explicitly disclose, but Ray teaches, the adjusted voltage including one or more of: an adjusted bit line (BL) bias voltage, or an adjusted source line (SL) voltage (by teaching that the source line voltage and sensing voltage or read voltage applied to a bit line (i.e., bit line bias voltage) during a read operation may be increased or decreased based on the difference in programming and read temperature [0027-0029] [0031] [0087-0088] [0092]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Regarding claim 5 and analogous claims 13 and 19:
The data storage system of claim 1 is made obvious by Getreuer in view of Kim in further view of Ray (Getreuer-Kim-Ray).
Getreuer further discloses, the VB including a bit line (BL), the BL including a string of cells electrically connected in series (by disclosing that the GCU (VB) includes a blocks from a plurality of dies and planes. Each block includes a plurality of word lines that connect the memory cells that make up each page. The blocks also include a plurality of bit lines that intersect a plurality of cells in series and may be controlled with various control lines like source lines [0052-0058] [Fig. 5]. A read operation is applied to a wordlines, and is therefore applied to a wordline of a GCU [0063-0064]. During a read operation, the memory cells (148) of a page of data may be read by applying a particular read voltage to the word line (170) of the page of data to read the memory cells [0064-0065]).
Getreuer does not explicitly disclose, but Ray teaches, the adjusted voltage to adjust a string current (Icell) of the string of cells (by teaching that the source line voltage controls a current that is sensed through a NAND string in order to determine the bit value read from a memory cell [0087], such that adjusting a voltage of the source line would adjust the current sensed through the NAND string, resulting in more accurate reading of the memory cells [0027-0028] [0031] [0045-0046] [See Fig. 7A]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Regarding claim 6:
The data storage system of claim 5 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses, the determination of the cross-temperature condition including determining that a read voltage associated with the VB has increased above a default read voltage (by teaching as seen in [Fig. 14], where a read temperature is higher than a program temperature, the threshold voltage shift is less (i.e. more negative) and where a read temperature is lower than a program temperature, the threshold voltage shift is greater (i.e. more positive), such that when it is applied to an existing read voltage value (i.e. default read voltage) it shifts the voltage up or down. In the case of this particular claim, the readings where the read temperature is lower than the program temperature would be associated with the VB having a read voltage increased above a default read voltage (i.e. including determining that a read voltage associated with the VB as increased above a default read voltage) [Fig. 14] [0119-0120]).
Getreuer does not explicitly disclose, but Ray teaches, the adjusted voltage to increase the Icell (by teaching that the source line voltage controls a current that is sensed through a NAND string in order to determine the bit value read from a memory cell [0087], such that adjusting a voltage of the source line would adjust the current sensed through the NAND string, resulting in more accurate reading of the memory cells [0027-0028] [0031] [0045-0046] [See Fig. 7A]. As seen in the examples giving specific program temperatures, read temperatures, and adjusted source line voltages, the decreased voltages on the source line in the high temperature program and low temperature read condition would result in higher gate to source overdrive voltages on the source side select gate (SGS) transistors, and therefore higher currents through the NAND string (i.e., those cells connected in series along BL0-BLX) and therefore higher cell current, as seen in [Fig. 3A] [0031] [0077]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures, such that in a high program temperature low read temperature condition, the source voltage is decreased, which results in an increase the current through a NAND string as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Regarding claim 7:
The data storage system of claim 5 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses, the determination of the cross-temperature condition including determining that a read voltage associated with the VB has decreased above a default read voltage (by teaching as seen in [Fig. 14], where a read temperature is higher than a program temperature, the threshold voltage shift is less (i.e. more negative) and where a read temperature is lower than a program temperature, the threshold voltage shift is greater (i.e. more positive), such that when it is applied to an existing read voltage value (i.e. default read voltage) it shifts the voltage up or down. In the case of this particular claim, the readings where the read temperature is higher than the program temperature would be associated with the VB having a read voltage decreased below a default read voltage (i.e. including determining that a read voltage associated with the VB as decreased below a default read voltage) [Fig. 14] [0119-0120]).
Getreuer does not explicitly disclose, but Ray teaches, the adjusted voltage to decrease the Icell (by teaching that the source line voltage controls a current that is sensed through a NAND string in order to determine the bit value read from a memory cell [0087], such that adjusting a voltage of the source line would adjust the current sensed through the NAND string, resulting in more accurate reading of the memory cells [0027-0028] [0031] [0045-0046] [See Fig. 7A]. As seen in the examples giving specific program temperatures, read temperatures, and adjusted source line voltages, the increased voltages on the source line in the low temperature program and high temperature read condition would result in lower gate to source overdrive voltages on the source side select gate (SGS) transistors, and therefore lower currents through the NAND string (i.e., those cells connected in series along BL0-BLX) and therefore lower cell current, as seen in [Fig. 3A] [0031] [0077]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures, such that in a low program temperature high read temperature condition, the source voltage is increased, which results in a decrease in the current through a NAND string as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Regarding claim 8 and analogous claims 14 and 20:
The data storage system of claim 1 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses, the VB including a plurality of physical blocks, the measured program temperature including an aggregation of program temperature values corresponding to respective ones of the plurality of physical blocks, the measured read temperature including an aggregation of read temperature values corresponding to respective ones of the plurality of physical blocks (by teaching that a GCU includes a plurality of physical blocks distributed across a plurality of planes and dies [0057-0058]. A temperature sensor (132) may sense the temperature of the SSD across multiple locations [0050], for example, across each die [0075]. The measured temperatures may include values aggregated across a plurality of sensors and times to create location weighted and time averaged values [0091]. Tprogram may be stored as the then measured Tcurrent [0121]. The temperatures are associated with a GCU or block or other granularity, and are stored when pages of a block of a GCU are programmed, and retrieved when pages of a block of a GCU are read (i.e., an aggregation of read temperature values corresponding to respective ones of the plurality of physical blocks) [0077] [0090-0091] [0124-0126] [0130] [Fig. 11]).
Claim 2-4, 10-12 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Getreuer-Kim-Ray in further view of US Patent Application Publication No. US 2023/0004297 A1 (Wan).
Regarding claim 2 and analogous claims 10 and 16:
The data storage system of claim 1 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses, wherein the VB includes a plurality of wordlines (WLs), the instructions, when executed by the at least one processor, causing the at least one processor to: perform a read operation at least in part by – applying a read voltage to a first WL of the plurality of WLs (by disclosing that the GCU (VB) includes a blocks from a plurality of dies and planes. Each block includes a plurality of word lines that connect the memory cells that make up each page. The blocks also include a plurality of bit lines that intersect each cell and may be controlled with various control lines like source lines [0052-0058] [Fig. 5]. A read operation is applied to a wordlines, and is therefore applied to a wordline of a GCU [0063-0064]. During a read operation, the memory cells (148) of a page of data may be read by applying a particular read voltage to the word line (170) of the page of data to read the memory cells [0064-0065]. The particular read voltage is determined by the CTMC (200) [Fig. 17], which may be firmware executed by the processors of the SSD controller (112) [0073] [0077-0078]).
Getreuer does not explicitly disclose, but Wan teaches the VB includes a plurality of virtual wordlines (VWLs), such that read voltages are applied to a VWL of the plurality of VWLs (by teaching that a super block (650) (i.e., analogous to the GCU unit of Getreuer and Applicant’s VB, as it teaches that a blocks from across a plurality of planes may be formed into a super block [0096]) may have a plurality of super pages (652), which are pages with the same page index in each of the blocks (103) across a plurality of planes (101) that form the super block (650) [0096]. The entire data of a super page may be read and written in parallel in order to improve efficiency of the memory [0096]. Each page is understood to be formed from the memory cells of a single word line [0062]. Accordingly, a super page is analogous to Applicant’s disclosed VWL (“The VWL may include the WL… from a block… of each of the planes [Applicant’s Specification, 0066]) as it is a page (i.e., word line) from each of a plurality of blocks across a plurality of planes [see Fig. 8])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read operation with adjusted read voltages on a word line of a page of a GCU as taught by Getreuer to be performed across all wordlines of a super page during a read to all the data of the super page of the super block (i.e. GCU as taught by Getreuer) performed simultaneously as taught by Wan.
One of ordinary skill in the art would have been motivated to make this modification because reading the data of an entire super page simultaneously is more efficient and increases throughput as taught by Wan in [0096].
Regarding claim 3 and analogous claims 11 and 17:
The data storage system of claim 1 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses wherein the VB includes a plurality of wordlines (WLs) and a plurality of bitlines (BLs), the instructions, when executed by the at least one processor, causing the at least one processor to: perform a read operation at least in part by – applying a read voltage to a first WL of the plurality of WLs (by disclosing that the GCU (VB) includes a blocks from a plurality of dies and planes. Each block includes a plurality of word lines that connect the memory cells that make up each page. The blocks also include a plurality of bit lines that intersect each cell and may be controlled with various control lines like source lines [0052-0058] [Fig. 5]. A read operation is applied to a wordlines, and is therefore applied to a wordline of a GCU [0063-0064]. During a read operation, the memory cells (148) of a page of data may be read by applying a particular read voltage to the word line (170) of the page of data to read the memory cells [0064-0065]. The particular read voltage is determined by the CTMC (200) [Fig. 17], which may be firmware executed by the processors of the SSD controller (112) [0073] [0077-0078]).
Getreuer does not explicitly disclose, but Wan teaches the VB includes a plurality of virtual wordlines (VWLs), such that read voltages are applied to a VWL of the plurality of VWLs (by teaching that a super block (650) (i.e., analogous to the GCU unit of Getreuer and Applicant’s VB, as it teaches that a blocks from across a plurality of planes may be formed into a super block [0096]) may have a plurality of super pages (652), which are pages with the same page index in each of the blocks (103) across a plurality of planes (101) that form the super block (650) [0096]. The entire data of a super page may be read and written in parallel in order to improve efficiency of the memory [0096]. Each page is understood to be formed from the memory cells of a single word line [0062]. Accordingly, a super page is analogous to Applicant’s disclosed VWL (“The VWL may include the WL… from a block… of each of the planes [Applicant’s Specification, 0066]) as it is a page (i.e., word line) from each of a plurality of blocks across a plurality of planes [see Fig. 8])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read operation with adjusted read voltages on a word line of a page of a GCU as taught by Getreuer to be performed across all wordlines of a super page during a read to all the data of the super page of the super block (i.e. GCU as taught by Getreuer) performed simultaneously as taught by Wan.
One of ordinary skill in the art would have been motivated to make this modification because reading the data of an entire super page simultaneously is more efficient and increases throughput as taught by Wan in [0096].
Getreuer in view of Wan do not explicitly disclose, but Ray teaches wherein the adjusted voltage is an adjusted BL bias voltage and the instructions, when executed by the at least one processor, causing the at least one processor to: applying the adjusted BL bias voltage to one or more of the plurality of BLs (by teaching that the source line voltage and sensing voltage or read voltage applied to a bit line (i.e., bit line bias voltage) during a read operation may be increased or decreased based on the difference in programming and read temperature [0027-0029] [0031] [0087-0088] [0092].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Regarding claim 4 and analogous claims 12 and 18:
The data storage system of claim 1 is made obvious by Getreuer-Kim-Ray.
Getreuer further discloses wherein the VB includes a plurality of wordlines (WLs) and a plurality of physical blocks, the instructions, when executed by the at least one processor, causing the at least one processor to: perform a read operation at least in part by – applying a read voltage to a first WL of the plurality of WLs (by disclosing that the GCU (VB) includes a blocks from a plurality of dies and planes. Each block includes a plurality of word lines that connect the memory cells that make up each page. The blocks also include a plurality of bit lines that intersect each cell and may be controlled with various control lines like source lines [0052-0058] [Fig. 5]. A read operation is applied to a wordlines, and is therefore applied to a wordline of a GCU [0063-0064]. During a read operation, the memory cells (148) of a page of data may be read by applying a particular read voltage to the word line (170) of the page of data to read the memory cells [0064-0065]. The particular read voltage is determined by the CTMC (200) [Fig. 17], which may be firmware executed by the processors of the SSD controller (112) [0073] [0077-0078]).
Getreuer does not explicitly disclose, but Wan teaches the VB includes a plurality of virtual wordlines (VWLs), such that read voltages are applied to a VWL of the plurality of VWLs (by teaching that a super block (650) (i.e., analogous to the GCU unit of Getreuer and Applicant’s VB, as it teaches that a blocks from across a plurality of planes may be formed into a super block [0096]) may have a plurality of super pages (652), which are pages with the same page index in each of the blocks (103) across a plurality of planes (101) that form the super block (650) [0096]. The entire data of a super page may be read and written in parallel in order to improve efficiency of the memory [0096]. Each page is understood to be formed from the memory cells of a single word line [0062]. Accordingly, a super page is analogous to Applicant’s disclosed VWL (“The VWL may include the WL… from a block… of each of the planes [Applicant’s Specification, 0066]) as it is a page (i.e., word line) from each of a plurality of blocks across a plurality of planes [see Fig. 8])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read operation with adjusted read voltages on a word line of a page of a GCU as taught by Getreuer to be performed across all wordlines of a super page during a read to all the data of the super page of the super block (i.e. GCU as taught by Getreuer) performed simultaneously as taught by Wan.
One of ordinary skill in the art would have been motivated to make this modification because reading the data of an entire super page simultaneously is more efficient and increases throughput as taught by Wan in [0096].
Getreuer in view of Wan do not explicitly disclose, but Ray teaches wherein the adjusted voltage is an adjusted SL bias voltage and the instructions, when executed by the at least one processor, causing the at least one processor to: applying the adjusted SL bias voltage to one or more of the plurality of physical blocks BLs (by teaching that the source line voltage and sensing voltage or read voltage applied to a bit line (i.e., bit line bias voltage) during a read operation may be increased or decreased based on the difference in programming and read temperature [0027-0029] [0031] [0087-0088] [0092].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltages adjusted in a cross-temperature read operation as taught by Getreuer to include modifying the source line voltage and bit line voltage according to the program and read temperatures as taught by Ray.
One of ordinary skill in the art would have been motivated to make this modification because it would reduce the cross-temperature effects to the threshold voltages, which increase data errors as taught by Ray in [0026] [0031] [0087-0088].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2020/0333976 A1 (Cariello) – discloses performing temperature optimizations on reads of superblocks and uses distributed temperature sensors to determine the temperature.
US Patent Application Publication No. US 2019/0392907 A1 (Her) – discloses performing a normal read vs. a cross-temperature read operation.
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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