DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because the abstract is a recitation of the claims. The claims themselves are the legal bounds and legal description of the invention. The use of the legal phraseology of the claims should be avoided when writing the abstract. The abstract itself should be a short and concise summarization of the invention in its entirety, or at least the key features of the invention that can be summarized in the allotted space. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 8, 9, 12, 15, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yudkovich et al. (US PGPub 2024/0185940, hereafter referred to as Yudkovich) in view of Tian et al. (US PGPub 2023/0420053, hereafter referred to as Tian).
Regarding claim 1, Yudkovich teaches a data storage system comprising: a memory device including a block, the block including a plurality of wordlines (WLs) (Fig. 4A-4D and Paragraph [0091], shows various parts of the memory device including what a block composed of word lines looks like), non-transitory computer readable media storing instructions thereon, and at least one processor (Paragraph [0111], states a processor and instructions that would need to be stored on a computer readable medium do exist), wherein the instructions, when executed by the at least one processor, cause the at least one processor to: detect errors associated with the block (Paragraphs [0112]-[0113], describe the process of performing health mitigation which first involves decoding statistics which can mean determining an error rate associated with a block), determine, based at least in part on the detected errors, a cross-temperature condition (Fig. 7-8 and Paragraph [0116], states that after the decoding statistics can be collected for each set (block) which can include the cross-temperature), and perform a read operation at least in part by - applying a read voltage to a first WL of the plurality of WLs, applying the Vpassr to one or more remaining WLs of the plurality of WLs (Paragraphs [0126]-[0128], states that one of the responses to determining errors is to perform a direct look ahead read which involves reading a word line with a particular read threshold voltage (it should be noted this is a standard procedure when performing a read) as well as applying a pass voltage to adjacent word lines). Yudkovich does not explicitly teach adjusting a pass through voltage (Vpassr) based on the determined cross-temperature condition.
Tian teaches adjusting a pass through voltage (Vpassr) based on the determined cross-temperature condition (Paragraph [0131], states that depending on the cross temperature the pass voltage can be adjusted). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yudkovich to adjust the pass voltage as taught in Tian so that the reliability of a memory device is improved (Tian, Paragraph [0051]).
Regarding claim 2, Yudkovich and Tian teach all the limitations to claim 1. Yudkovich further teaches the determination of the cross-temperature condition including: determining a number of the detected errors meets one or more error criteria (Fig. 7 and Paragraph [0113], the statistics, which include error, can be collected and action can be taken if the errors are great enough (meet an error criteria. It should be noted the claims do not specify what the criteria is)), responsive to determining the number of detected errors meets the one or more error criteria, measuring a temperature of the memory device (Fig. 7-8 and Paragraph [0116], as stated in the rejection to claim 1, the statistics that can be collected after determining errors are cross-temperature and temperature meaning the temperature of the memory device would need to be measured to determine both statistics), and responsive to measuring the temperature, determining the cross-temperature condition (Paragraph [0116], as stated previously). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Yudkovich and Tian teach all the limitations to claim 1. Yudkovich further teaches the block including a bit line (BL), the BL including a string of cells electrically connected in series, each cell of the string of cells including a gate, a first cell of the string of cells being connected to the first WL, the first cell storing data (Fig. 4D and Paragraph [0091], show the composition of a block of memory and shows the wordlines, bit lines, cells, gates, etc. It should also be noted this is a standard configuration of flash memory of which both the references and application use). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 8, 9, and 12, claims 8, 9, and 12 are the method claims associated with claims 1, 2, and 5. Since Yudkovich and Tian teach all the limitations to claims 1, 2, and 5, they also teach all the limitations to claims 8, 9, and 12; therefore the rejections to claims 1, 2, and 5 also apply to claims 8, 9, and 12.
Regarding claims 15, 16, and 19, claims 15, 16, and 19 are the computer readable medium claims associated with claims 1, 2, and 5. Since Yudkovich and Tian teach all the limitations to claims 1, 2, and 5, they also teach all the limitations to claims 15, 16, and 19; therefore the rejections to claims 1, 2, and 5 also apply to claims 15, 16, and 19.
Claims 3, 4, 10, 11, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yudkovich and Tian as applied to claims 1 above, and further in view of Muchherla et al. (US PGPub 2022/0277798, hereafter referred to as Muchherla).
Regarding claim 3, Yudkovich and Tian teach all the limitations to claim 1. Yudkovich and Tian do not teach the determination of the cross-temperature condition including determining that a read threshold voltage associated with the block has increased above a previous read threshold voltage, the adjusting the Vpassr including increasing the Vpassr.
Muchherla teaches the determination of the cross-temperature condition including determining that a read threshold voltage associated with the block has increased above a previous read threshold voltage, the adjusting the Vpassr including increasing the Vpassr (Paragraphs [0080]-[0082], states that the pass voltage can be changed to match a change (increase or decrease) in the read voltage of the block. Paragraphs [0023]-[0024], this change can be due to temperature). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yudkovich and Tian to utilize the pass voltage adjustment method taught in Muchherla so to gain an improved performance of the memory sub-system by mitigating read disturb by reducing the pass-through voltage used during read operations performed by the memory sub-system (Muchherla, Paragraph [0031]).
Regarding claim 4, Yudkovich and Tian teach all the limitations to claim 1. Yudkovich and Tian do not teach the determination of the cross-temperature condition including determining that a read threshold voltage associated with the block has decreased below a previous read threshold voltage, the adjusting the Vpassr including decreasing the Vpassr.
Muchherla teaches the determination of the cross-temperature condition including determining that a read threshold voltage associated with the block has decreased below a previous read threshold voltage, the adjusting the Vpassr including decreasing the Vpassr (Paragraphs [0080]-[0082], states that the pass voltage can be changed to match a change (increase or decrease) in the read voltage of the block. Paragraphs [0023]-[0024], this change can be due to temperature). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yudkovich and Tian to utilize the pass voltage adjustment method taught in Muchherla so to gain an improved performance of the memory sub-system by mitigating read disturb by reducing the pass-through voltage used during read operations performed by the memory sub-system (Muchherla, Paragraph [0031]).
Regarding claims 10 and 11, claims 10 and 11 are the method claims associated with claims 3 and 4. Since Yudkovich, Tian, and Muchherla teach all the limitations to claims 3 and 4, they also teach all the limitations to claims 10 and 11; therefore the rejections to claims 3 and 4 also apply to claims 10 and 11.
Regarding claims 17 and 18, claims 17 and 18 are the computer readable medium claims associated with claims 3 and 4. Since Yudkovich, Tian, and Muchherla teach all the limitations to claims 3 and 4, they also teach all the limitations to claims 17 and 18; therefore the rejections to claims 3 and 4 also apply to claims 17 and 18.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yudkovich and Tian as applied to claims 5 above, and further in view of Jain (US PGPub 2022/0075687).
Regarding claim 6, Yudkovich and Tian teach all the limitations of claim 5. Yudkovich and Tian do not explicitly teach the read operation being performed to read the data from the first cell and the read operation including applying a BL bias voltage to the BL.
Jain teaches the read operation being performed to read the data from the first cell and the read operation including applying a BL bias voltage to the BL (Paragraph [0128], states that the bias voltage that is applied to a bit line can be adjusted for a read operation meaning the read operation is performed by applying the bit line bias voltage). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yudkovich and Tian to perform a read operation using the bit line bias voltage as taught in Jain so to reduce a number of read errors by compensating for the low cell current from one or more of the storage (Jain, Paragraph [0128]).
Regarding claim 13, claim 13 are the method claim associated with claim 6. Since Yudkovich, Tian, and Jain teach all the limitations to claim 6, they also teach all the limitations to claim 13; therefore the rejection to claim 6 also apply to claim 13.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yudkovich and Tian as applied to claims 5 above, and further in view of Yang et al. (US PGPub 2019/0295667, hereafter referred to as Yang).
Regarding claim 7, Yudkovich and Tian teach all the limitations of claim 5. Yudkovich and Tian do not explicitly teach the adjusted Vpassr to adjust a string current (Icell) of the string of cells based on the determined cross-temperature condition.
Yang teaches the adjusted Vpassr to adjust a string current (Icell) of the string of cells based on the determined cross-temperature condition (Paragraph [0051], states that the pass voltage can be adjusted with temperature and as a consequence the string current can be reduced/adjusted). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yudkovich and Tian to utilize the pass voltage adjustment of Yang so variations in the resistance of a NAND string and the current through the NAND string due to the temperature dependency of unselected memory cells are reduced (Yang, Paragraph [0004]).
Regarding claim 14, claim 14 is the method claim associated with claim 7. Since Yudkovich, Tian, and Yang teach all the limitations to claim 7, they also teach all the limitations to claim 14; therefore the rejection to claim 7 also apply to claim 14.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yudkovich and Tian as applied to claim 19 above, and further in view of Jain and Yang.
Regarding claim 20, claim 20 is the computer readable medium claim associated with claims 6 and 7. Since Yudkovich, Tian, Jain, and Yang teach all the limitations to claims 6 and 7, they also teach all the limitations to claim 20; therefore the rejections to claims 6 and 7 also apply to claim 20.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
Prosecution Insights