DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the rank information" in Line 2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the claim was intended to refer to the target rank information, for which there is antecedent basis, or is referring to an entirely different rank information. For the purposes of examination, the claim shall be interpreted as simply “rank information”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of of U.S. Patent No. 12,333,169 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,333,169 B2 (see right column) anticipates the claims of the instant application 19/224,056 (see left column).
Instant Application 19/224,056
US Patent 12,333,169 B2
(Parent Application 18/304,813)
1. A multi-rank memory device associated with a memory controller, the multi- rank memory device comprising:
a plurality of memory ranks sharing a signal line; and
a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks,
wherein the multi-rank memory device is configured to:
receive, from the memory controller via the signal line, a memory operation comprising target rank information associated with a target memory rank determined by the memory controller, the memory operation including a read operation or a write operation on the target memory rank among the plurality of memory ranks,
compare the target rank information received from the memory controller with the ODT information of the plurality of memory ranks stored in the nonvolatile memory device,
based on a result of the comparison, determine the target memory rank and one or more non-target memory ranks among the plurality of memory ranks, and
set an ODT value of at least one non-target memory rank among the one or more non- target memory ranks.
1. A memory system comprising:
a host system comprising a memory controller configured to control a read operation or a write operation for a plurality of memory ranks configured to share a signal line; and
a multi-rank memory device comprising a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks,
wherein the memory controller is further configured to determine a target rank to be read or written, and transmit a read or write command comprising information about the determined target rank via the signal line, to the multi-rank memory device,
wherein the multi-rank memory device is further configured to perform a comparison of the ODT information of the plurality of memory ranks stored in the nonvolatile memory device with the information about the determined target rank received from the memory controller, determine a memory rank corresponding to the determined target rank and a memory rank corresponding to a non-target rank based on a result of the comparison and set an ODT value of the non-target rank, wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
2. The multi-rank memory device of claim 1 is further configured to: store, in the nonvolatile memory device, the ODT information including first information of the target memory rank and second information of the one or more non-target memory ranks.
3. The multi-rank memory device of claim 2 is further configured to: change ODT values of the plurality of memory ranks, based on the first information and the second information, based on the read operation for the multi-rank memory device being performed.
3. The memory system of claim 2, wherein the multi-rank memory device is further configured to change ODT values of the plurality of memory ranks, based on the first information and the second information, when a read operation for the multi-rank memory device is performed.
4. The multi-rank memory device of claim 2 is further configured to: change ODT values of the plurality of memory ranks, based on the first information and the second information, based on the write operation for the multi-rank memory device being performed.
4. The memory system of claim 2, wherein the multi-rank memory device is further configured to change ODT values of the plurality of memory ranks, based on the first information and the second information, when a write operation for the multi-rank memory device is performed.
5. The multi-rank memory device of claim 1 is further configured to: perform a refresh operation of the target memory rank.
5. The memory system of claim 1, wherein the multi-rank memory device is further configured to perform a refresh operation of the target rank
6. The multi-rank memory device of claim 1 is further configured to perform a fusing operation of the rank information to the nonvolatile memory device.
6. The memory system of claim 1, wherein the multi-rank memory device is further configured to perform a fusing operation of the rank information to the nonvolatile memory device.
7. The multi-rank memory device of claim 1, wherein the ODT value of the at least one non-target memory rank corresponding to the write operation is different from the ODT value of the non-target memory rank during the read operation.
1. …
wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
8. The multi-rank memory device of claim 1, wherein the signal line is a command/address signal line.
1. … transmit a read or write command comprising information about the determined target rank via the signal line, to the multi-rank memory device…
9. A method of operating a multi-rank memory device associated with a memory controller, the multi-rank memory device including a plurality of memory ranks sharing a signal line and a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks, the method comprising:
receiving, from the memory controller via the signal line, a memory operation comprising the plurality of memory ranks, the memory operation including a read operation or a write operation on a target memory rank among the plurality of memory ranks;
comparing the target rank information received from the memory controller with the ODT information of the memory ranks stored in the nonvolatile memory device;
determining the target memory rank and one or more non-target memory ranks among the plurality of memory ranks, based on a result of the comparison; and
setting an ODT value of at least one non-target memory rank among the one or more non- target memory ranks.
7. A method of operating a memory system including a plurality of memory ranks configured to share a signal line, the method comprising:
controlling, by a host system comprising a memory controller, a read operation or a write operation for a plurality of memory ranks configured to share the signal line; and
storing on-die termination (ODT) information of the plurality of memory ranks in a storage of a multi-rank memory device comprising a nonvolatile memory device configured to store the rank information of the plurality of memory ranks, wherein the controlling of the read or write operation for the plurality of memory ranks comprises:
determining a target rank to be read or written, and transmitting a read or write command comprising information about the determined target rank via the signal line, to the multi-rank memory device; and
comparing the ODT information of the plurality of memory ranks stored in the nonvolatile memory device with the information about the determined target rank received from the memory controller;
determining a memory rank corresponding to the determined target rank and a memory rank corresponding to a non-target rank based on a result of the comparing; and
setting an ODT value of the non-target rank, wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
10. The method of claim 9 further comprises: changing ODT values of the memory ranks, based on the first information and the second information, based on the read operation for the multi-rank memory device is performed.
9. The method of claim 8, wherein the controlling of the read or write operation for the plurality of memory ranks comprises: changing ODT values of the plurality of memory ranks, based on the first information and the second information, when a read operation for the multi-rank memory device is performed.
11. The method of claim 9 further comprises: changing ODT values of the plurality of memory ranks, based on the first information and the second information, based on the write operation for the multi-rank memory device being performed.
9. The method of claim 8, wherein the controlling of the read or write operation for the plurality of memory ranks comprises: changing ODT values of the plurality of memory ranks, based on the first information and the second information, when a read operation for the multi-rank memory device is performed.
12. The method of claim 9, wherein the signal line is a command/address signal line.
10. The method of claim 8, further comprising: performing an enable or disable operation of a command/address signal line receiver connected to a command/address signal line, based on the target or non-target information; and performing an enable or disable operation of a transmit data bus receiver connected to a data bus, based on the target or non-target information.
13. The method of claim 9 further comprises: receiving a refresh command from the memory controller; and performing a refresh operation of the target memory rank.
11. The method of claim 7, further comprising: transmitting a refresh command to a first rank of the multi-rank memory by a host system, wherein the controlling of the read or write operation for the plurality of memory ranks further comprises receiving the refresh command and performing a refresh operation of the first rank.
14. The method of claim 9 further comprises: storing, in the nonvolatile memory device, the ODT information including first information of the target memory rank and second information of the one or more non-target memory ranks.
8. The method of claim 7, wherein the controlling of the read or write operation for the plurality of memory ranks comprises: storing first information about the target rank and second information about the plurality of memory ranks except the target rank.
15. The method of claim 14 wherein the storing of the ODT information comprises: performing a fusing operation of the first information of the target memory rank or the second information of the one or more non-target memory ranks.
13. The method of claim 12, wherein the controlling of the read or write operation for the plurality of memory ranks further comprises performing the fusing operation of the information of the first rank or the second rank to a nonvolatile memory device.
16. The method of claim 9, wherein the ODT value of the non-target memory rank during the write operation is different from the ODT value of the non-target memory rank during the read operation.
7. …
wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
17. A method of operating memory controller associated with a multi-rank memory device including a plurality of memory ranks sharing a signal line and a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks, the method comprising:
determining a target memory rank associated with a memory operation, the memory operation including a read operation or a write operation on the target memory rank among the plurality of memory ranks; and
setting an ODT value of at least one non-target memory rank among one or more non- target memory ranks among the plurality of memory ranks, wherein the setting of the ODT value of the at least one non-target memory rank comprises:
transmitting, to the multi-rank memory device via the signal line, the memory operation comprising target rank information associated with the target memory rank,
wherein the one or more non-target memory ranks among the plurality of memory ranks are identified, by the multi-rank memory device, by comparing the target rank information with the ODT information stored in the nonvolatile memory device.
7. A method of operating a memory system including a plurality of memory ranks configured to share a signal line, the method comprising:
controlling, by a host system comprising a memory controller, a read operation or a write operation for a plurality of memory ranks configured to share the signal line; and
storing on-die termination (ODT) information of the plurality of memory ranks in a storage of a multi-rank memory device comprising a nonvolatile memory device configured to store the rank information of the plurality of memory ranks, wherein the controlling of the read or write operation for the plurality of memory ranks comprises:
determining a target rank to be read or written, and transmitting a read or write command comprising information about the determined target rank via the signal line, to the multi-rank memory device; and
comparing the ODT information of the plurality of memory ranks stored in the nonvolatile memory device with the information about the determined target rank received from the memory controller;
determining a memory rank corresponding to the determined target rank and a memory rank corresponding to a non-target rank based on a result of the comparing; and
setting an ODT value of the non-target rank, wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
18. The method of claim 17, wherein the ODT information including first information of the target memory rank and second information of the one or more non-target memory ranks.
8. The method of claim 7, wherein the controlling of the read or write operation for the plurality of memory ranks comprises: storing first information about the target rank and second information about the plurality of memory ranks except the target rank.
19. The method of claim 17, wherein the ODT value of the at least one non-target memory rank corresponding to the write operation is different from the ODT value of the non- target memory rank during the read operation.
7. …
wherein the ODT value of the non-target rank during the write operation is different from the ODT value of the non-target rank during the read operation.
20. The method of claim 17, wherein the ODT information is stored in the nonvolatile memory device by a fusing operation of the rank information to the nonvolatile memory device.
13. The method of claim 12, wherein the controlling of the read or write operation for the plurality of memory ranks further comprises performing the fusing operation of the information of the first rank or the second rank to a nonvolatile memory device.
Allowable Subject Matter
Claims 1-5 and 7-20 are allowed. Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Independent claim 1 recites the following limitations with features highlighted in combination with the other limitations of the claims most overcome the prior art of record:
“A multi-rank memory device associated with a memory controller, the multi- rank memory device comprising:
a plurality of memory ranks sharing a signal line; and
a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks, wherein the multi-rank memory device is configured to:
receive, from the memory controller via the signal line, a memory operation comprising target rank information associated with a target memory rank determined by the memory controller, the memory operation including a read operation or a write operation on the target memory rank among the plurality of memory ranks,
compare the target rank information received from the memory controller with the ODT information of the plurality of memory ranks stored in the nonvolatile memory device,
based on a result of the comparison, determine the target memory rank and one or more non-target memory ranks among the plurality of memory ranks, and
set an ODT value of at least one non-target memory rank among the one or more non- target memory ranks.”
The most relevant prior art does not appear to teach or suggest the highlighted limitations in combination with the other recited limitations. The closest prior art is Moon et al. (US 2019/0304517 A1) and Cox et al. (US 2019/039886 A1). Moon et al. teaches a two-rank structure divides memory system into a target rank and non-target rank, and the memory controller may receive, from the processor core of the SOC, a memory request for memory access to the rank A and rank B which include read/write requests. While Moon et al. teaches ODT state information of the ODT circuit of the memory device utilizes mode register 310 that stores OD state/setting information, which reads on the claimed ODT information of the plurality of memory ranks stored in the nonvolatile memory device, this stored information is not compared to the received target rank information in order to make a determination as to which is the target memory rank and which are the non-target memory ranks. Moon et al. teaches a plurality of memory ranks sharing a signal line; and a nonvolatile memory device configured to store on-die termination (ODT) information of the plurality of memory ranks, wherein the multi-rank memory device is configured to: receive, from the memory controller via the signal line, a memory operation comprising target rank information associated with a target memory rank determined by the memory controller, the memory operation including a read operation or a write operation on the target memory rank among the plurality of memory ranks, and even further teaches set an ODT value of at least one non-target memory rank among the one or more non- target memory ranks. However, Moon et al. is silent with regards to the comparing step using the received target rank information and previously stored ODT information to identify which ranks are target vs. non-target. Cox et al. teaches monitoring selected signal lines of the command bus to determine an on-die termination (ODT) trigger. During a multicycle command, if the CS signal line is driven low for both the first and command cycles, then the DRAM device is identified as a non-target device. Thus, while Cox et al. teaches receive, from the memory controller via the signal line, a memory operation comprising target rank information associated with a target memory rank determined by the memory controller, the memory operation including a read operation or a write operation on the target memory rank among the plurality of memory ranks and using target rank information to determine the target memory rank and one or more non-target memory ranks among the plurality of memory ranks, the determination is not being made based on a result of a comparison between the target rank info and previously stored ODT information. While one or more reasons are offered citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Moon et al. and Cox et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Claims 2-8 depend upon claim 1, and thus, is allowable for at least the same reasons as outlined above.
Claims 9 and 17 recites subject matter substantially similar to that as recited in claim 1, and thus, is found to be allowable for the reasons discussed supra. Claims 10-16 and 18-20 depend upon claims 9 and 17, respectively, and thus, is allowable for at least the same reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhao et al. (US 2021/0326295 A1) teaches an ODT command is transmitted from a NAND controller comprising a command type field and first/second address field, one of which may be a LUN address to identify which LUN of the storage device is selected to enable its ODT according to the ODT command.
Zhang et al. (US 2022/0365708 A1) teaches setting target ODT values, and restoring values to a preset non-target ODT value when a read/write operation is completed.
Son et al. (US 2018/0342274 A1) teaches enabling the ODT circuits of a write target memory rank and non-target memory ranks during a write operation and disabling the ODT circuit of a read target memory rank while enabling the ODT circuits of non-target memory ranks during a read operation.
Hwang et al. (US 2022/0057965 A1) teaches receiving an ODT flag that indicates whether an ODT operation is possible for a non-target memory device.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
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