DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 4, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, the language indicates that the unmapping of the one or more physical page addresses occurs “… in response to receiving the command”. However, parent claim 14 has previously recited that the unmapping of the one or more physical page addresses occurs “…in response to determining that the data has been read from the one or more physical page addresses”. The Examiner has interpreted the claims such that the unmapping will occur according to the first claim limitation requirement found in claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Traister et al. (US# 2013/0212317).
Regarding claim 1, Traister et al. teaches one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system to [0016, lines 3-7: processor and memory/code for operations]: receive an indication of a range of addresses for storing a memory image of a host device, the range of addresses of an address space of the memory system [0012, lines 16-21]; receive data from the host device associated with the range of addresses; and write the data to one or more memory arrays of the memory system according to at least one parameter associated with storing the memory image [0025, lines 11-21; see also 0022, lines 1-6 for further mapping].
Regarding claim 2, Traister et al. teaches wherein, to write the data, the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: write the data to a plurality of consecutive physical page addresses of the one or more memory arrays [0025, lines 5-8; top “consecutive” 4GB is evicted], wherein writing the data to the plurality of consecutive physical page addresses is according to a compressed (space-saving) [0022, lines 1-6] logical-to-physical mapping table [overlapping partitions] associated with the range of addresses, and wherein the at least one parameter associated with storing the memory image comprises a compression of the logical-to-physical mapping table [0023, lines 1-8].
Regarding claim 4, Traister et al. teaches wherein, to receive the indication, the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: receive a configuration indicating a logical unit number (LUN) for storing the memory image, wherein the LUN comprises the range of addresses [hiber file is always stored in same “top” location (span of addresses) after “top” location data is evicted, thus rendering the span of addresses as a singular first logical area different from the remainer of the sdd; 0025, lines 11-21].
Regarding claim 5, Traister et al. teaches wherein, to receive the indication, the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: receive a command to associate the range of addresses with the memory image [Fig. 2 & 3; 0023 and 0024].
Regarding claim 6, Traister et al. teaches wherein, to receive the indication, the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: receive a command indicating that the host device is entering a suspend (S3) state [0020, liens 4-9; 0025, lines 17-20]; and monitor addresses (for hibernation file storage in ssd) accessed while the host device is in the suspend state [during transition to S4; 0025, lines 14-20].
Regarding claim 7, Traister et al. teaches a memory system, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system to [0016, lines 3-7: processor and memory/code for operations]: receive an indication of a range of addresses for storing a memory image of a host device, the range of addresses of an address space of the memory system [0012, lines 16-21]; receive one or more requests from the host device for data stored in the range of addresses (as part of exiting of hibernation mode); and read the data from one or more physical page addresses of one or more memory arrays according to at least one parameter associated with the range of addresses being associated with storing the memory image [0026; read operation occurring at a time after data read from physical addresses on ssd and loaded onto DRAM].
Regarding claim 8, Traister et al. teaches wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: retrieve, in response to determining a power on condition [exiting of hibernation state] of the memory system, a logical-to-physical mapping table associated with the range of addresses, wherein reading the data from the one or more physical page addresses is according to the logical-to- physical mapping table, and wherein the at least one parameter comprises the logical-to- physical mapping table [0026 (exit S4 state; 0022-0023].
Regarding claim 9, Traister et al. teaches to read a subset of the data from a physical page address of the one or more physical page addresses prior to receiving a command indicating to read the subset of the data, wherein the at least one parameter comprises reading the subset of the data from the physical page address prior to receiving the command indicating to read the subset of the data [exit hibernation reads all subset suspended to disk back to DRAM before specific commands to read the subsets; 0026].
Regarding claim 10, Traister et al. teaches wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: suppress a transition to a low power state in response to receiving the one or more requests from the host device for data stored in the range of addresses [S3 state is suppressed while in S4 state (transition from S3 to S4); as well as after the wake up process; 0027, lines 16-21].
Claim 11 recites language similar to that of claim 4, and is rejected for the same reasons as claim 4.
Claim 12 recites language similar to that of claim 5, and is rejected for the same reasons as claim 5.
Claim 13 recites language similar to that of claim 6, and is rejected for the same reasons as claim 5.
Claim 14 recites language similar to that of claim 1, and is rejected for the same reasons as claim 1, including to unmap the one or more physical page addresses in response to determining that the data has been read from the one or more physical page addresses [eviction, 0026, lines 10-15].
Regarding claim 15, Traister et al. teaches wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: receive a command to read second data from an address outside of the range of addresses, wherein unmapping the one or more physical page addresses is in response to receiving the command [any operation occurring after eviction after hibernation mode exit; 0026 and 0027, lines 1-8].
Claim 16 recites language similar to that of claim 10, and is rejected for the same reasons as claim 10.
Claim 17 recites language similar to that of claim 4, and is rejected for the same reasons as claim 4.
Claim 18 recites language similar to that of claim 5, and is rejected for the same reasons as claim 5.
Claim 19 recites language similar to that of claim 6, and is rejected for the same reasons as claim 6.
Regarding claim 20, Traister et al. teaches wherein at least one of the one or more memories comprises a non-volatile memory [ssd, 0014, lines 3-4].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Traister et al. (US# 20130212317) in view of Nishikubo et all. (US# 20170177235).
Regarding claim 3, Traister et al. teaches using an ssd for hibernation systems [0014], but fails to teach what form the ssd may take. Nishikubo et al. teaches to write the data according to a first programming mode of a plurality of programming modes comprising a single-level cell (SLC) programming mode, a multiple level cell (MLC) programming mode, and a triple-level cell (TLC) programming mode, wherein the at least one parameter associated with storing the memory image comprises the first programming mode [hibernation write to ssd 0054; writing of data to storage types based on data size (parameter), 0078-0079]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Traister et al. to include the multiple types of ssd storage in order to store data more efficiently without wasting space [0079].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen teaches ssd hibernation. Thanos et al. teaches hibernation systems with SLC/MLC/TLC type storage areas.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/BRIAN R PEUGH/Primary Examiner, Art Unit 2133
Prosecution Insights