DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07-22-26 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 9 (amended)of current application(19/224,618) is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No.12,341,525. Although the claims at issue are not identical, they are not patentably distinct from each other because current claim is broader in scope re the processing of PLL states, having 2 of the three states, already patented.
19/224,618
US Pat 12,341,525
9. (Currently Amended) A system comprising: an integrated circuit including: processing circuitry includinge an oscillator circuit, wherein:;the oscillator circuit is capable of operating as a frequency-locked loop (FLL) in a first state; and the oscillator circuit is capable of operating as a phase-locked loop (PLL) in a second state.
1. An integrated circuit (IC), comprising: an oscillator circuit having a control input and a capacitor; and a control circuit having a control output coupled to the control input, the control circuit configured to generate a control signal to the control input of the oscillator circuit to cause: the oscillator circuit to be configured as a first frequency-locked loop in response to the control signal being in a first state, wherein the capacitor is charged during the first state; the oscillator circuit to be configured as a second frequency-locked loop in response to the control signal being in a second state, wherein the second frequency-locked loop is configured to receive a voltage from the capacitor; and the oscillator circuit to be configured as a phase-locked loop in response to the control signal being in a third state.
As shown by the claims above, the patented claims include the FLL and PLL states of operation
as claimed by the current application and In light of the above it would have been obvious to
one of ordinary skill in the art before the effective filing date of the claimed invention to have
recognized that the current claim is merely broader in scope for the oscillator circuit processing
for the PLL and FLL states of operation, as processing of control signal states is, for all intent and
purposes, in the claim already patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 and 21(new)-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gupta et al.(US 20190097641) of record.
The reference to Gupta et al discloses a PLL/FLL(osc circuit overall), see figure below with oscillator 110.
A control circuit with calibration logic(2)(part of the DFLL, see ¶(0038)), allows for a control signal to be developed to affect the control input of the oscillator via block 105. The oscillator circuit is configured as a FLL in response to the control signal (first state)causing S1(close), S2(open). The PLL will be functional as the control signal is in a second state(see ¶0042). The processing circuit includes the biasing and calibration logic that provides signals(CAL1,2) to the osc circuit(FLL/PLL components shown in figure 2.
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Re claim 21(new): The osc circuit is capable of operating on the PLL state when receiving a RefClk, see figure 2. Also, prior to the PLL/FLL initialization, the biasing of the VCO is operational with no RefCLK needed.
“[0022] Also disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method may include prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO”.
Re claim 22(new): as noted above: The processing circuit includes the biasing and calibration logic that provides signals to the osc circuit(FLL/PLL components shown in figure 22. The bus including the control signal lines to the PLL/FLL elements receiving the CAL1,2 signals and thus responsive to those signals.
Re claim 23(new):
In ¶[0022] prior action on the oscillator(biasing) state before the PLL/FLL action is provided for:
“[0022] Also disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method may include prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method may also include activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated, and deactivating the frequency locked loop and activating the phase locked loop.”
Re claim 24(new):
Regarding the input for the RefCLK input to the oscillator circuit via the PFD(134) input.
Also, the system IC has digital comm interface(120/122) with RefCLK input too.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (AAPA: NPL cited by applicants: IEEE Trans, On Circuits and Systems Regular Papers, Vo. 61, No 11, Nov 2014) of record.
The reference to Chen et al discloses a PLL/FLL, see figure below with oscillator VCO.
A control circuit with PR(part of the FLL, see figure 1 description), allows for a control signal to be developed to affect the control input of the oscillator via Switch between amp(V/I) and VCO. The oscillator circuit is configured as a FLL in response to the control signal (first state, Freq Tracking mode state)causing the SW to allow the FLL functionality . The PLL will be functional as the control signal is in a second state(see p.3279). The processing circuit including the CDR with Rec DATA sent downstream to communication system not shown.
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Allowable Subject Matter
Claims 1-8 and 17-20 are allowed.
Claims 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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