DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2015/0333735 to Elias et al. (“Elias”).
In reference to Claim 1, Elias discloses an integrated circuit device (See Figure 5 Number 402 and 404 and Paragraphs 2 and 37) comprising: a set of pins (See Figure 5 VBUS, USBDP, USBDN, and USBID and Paragraphs 37-38); a power control circuit (See Figure 5 Numbers 416, 506, 508, and 512 and SVID and Energy Management Driver and Paragraph 41) capable of causing the integrated circuit device to operate in a first power mode (See Paragraphs 15 and 38 [standby or sleep mode]) and a second power mode that is associated with greater power consumption than the first power mode (See Paragraphs 15 and 28 [normal operating mode]); and a detector circuit (See Figure 5 Numbers 406, 408, and 502 and Paragraphs 28, 34, and 37-38) that includes: a first input (See Figure 5 Number 414) coupled to a first pin of the set of pins (See Figure 5 ID); and a first output coupled to the power control circuit (See Figure 5 Number 504); wherein the detector circuit is capable of, in the first power mode: determining whether the first pin is shorted to ground (See Paragraphs 28, 33, and 67 [USB-OTG connects the ID pin to ground when a micro-A plug is inserted]); and based on the first pin being shorted to ground, causing a transition from the first power mode to the second power mode (See Paragraphs 28, 38-39, and 41).
In reference to Claim 2, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses that the set of pins is capable of coupling to a Universal Serial Bus (USB) On The Go (OTG) receptacle (See Figure 5 Micro-Conn and Paragraph 28); and the first pin is a USB OTG ID pin (See Paragraph 28).
In reference to Claim 3, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses that the detector circuit includes a second input (See Figure 5 Number 412) coupled to a second pin of the set of pins (See Figure 5 VBUS).
In reference to Claim 7, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses that the detector circuit is capable of determining whether the first pin is shorted to ground based on a voltage at the first input of the detector circuit (See Paragraphs 28, 33, and 67 [USB-OTG connects the ID pin to ground when a micro-A plug is inserted, and the detector will thus detect 0V at the first input]).
In reference to Claim 8, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses a transceiver (See Figure 5 Number 410 and Paragraphs 14, 20, 22, and 27) coupled to a subset of the set of pins (See Figure 5 USBDP and USBDN), wherein the transition from the first power mode to the second power mode includes transitioning the transceiver from an inactive state to an active state (See Paragraphs 30, 32-33, 36, 43, and 66).
In reference to Claim 9, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses a microcontroller that includes the power control circuit and the detector circuit (See Figure 5 Numbers 402 and 404), wherein the transition from the first power mode to the second power mode includes performing a boot process using the microcontroller (See Paragraphs 32 and 36 [complete shutdown will necessarily require some sort of boot process when returning to the normal mode of operation]).
In reference to Claim 10, Elias discloses the limitations as applied to Claim 1 above. Elias further discloses a power regulator coupled to the power control circuit (See Figure 5 Power Supply), wherein the transition from the first power mode to the second power mode includes enabling the power regulator (See Paragraphs 32-33 and 66 [firmware and driver responds to power, resume, and/or attach signals to remove power gating to, and thus enable, the transceiver; gating power cuts off output of the power regulator, and thus removing gating enables the regulator within the broadest reasonable interpretation of the term]).
In reference to Claim 11, Elias discloses an integrated circuit device (See Figure 5 Number 402 and 404 and Paragraphs 2 and 37) comprising: a microcontroller (See Figure 5 Number 402 and 404 and Paragraphs 2 and 37) that includes: a power control circuit (See Figure 5 Numbers 416, 506, 508, and 512 and SVID and Energy Management Driver and Paragraph 41) capable of causing the microcontroller to operate in a first mode (See Paragraphs 15 and 38 [standby or sleep mode]) and a second mode (See Paragraphs 15 and 28 [normal operating mode]); a set of pins (See Figure 5 VBUS, USBDP, USBDN, and USBID and Paragraphs 37-38); a transceiver (See Figure 5 Number 410 and Paragraphs 14, 20, 22, and 27) coupled to a subset of the set of pins (See Figure 5 USBDP and USBDN); a detector circuit (See Figure 5 Numbers 406, 408, and 502 and Paragraphs 28, 34, and 37-38) coupled to the power control circuit (See Figure 5) and to a first pin of the set of pins (See Figure 5 Number 414), wherein the detector circuit is capable of, in the first mode: determining whether the first pin is shorted to ground (See Paragraphs 28, 33, and 67 [USB-OTG connects the ID pin to ground when a micro-A plug is inserted]); and based on the first pin being shorted to ground, cause the power control circuit to cause a transition from the first mode to the second mode (See Paragraphs 28, 38-39, and 41).
In reference to Claim 12, Elias discloses the limitations as applied to Claim 11 above. Elias further discloses that the transceiver is enabled in the second mode and is not enabled in the first mode (See Paragraphs 30, 32-33, 36, 43, and 66).
In reference to Claim 13, Elias discloses the limitations as applied to Claim 12 above. Elias further discloses that the second mode is associated with operation of the transceiver as a Universal Serial Bus (USB) host (See Paragraphs 33 and 67 [a USB-OTG device that detects a grounded voltage at the ID pin must initially operate as a host device]).
In reference to Claim 14, Elias discloses the limitations as applied to Claim 13 above. Elias further discloses the first pin is a USB OTG ID pin (See Paragraph 28).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elias as applied to Claims 1 and 11 above, and further in view of “MIC2555 USB-OTG Transceiver” by Micrel, Inc. (“MIC2555).
In reference to Claims 4-6, Elias discloses the limitations as applied to Claim 1 above. Elias is silent as to the particular structure of the detector circuit, and does not explicitly disclose that the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow from the second input to the first input, as in Claim 4; that the detector circuit includes a resistor coupled between the second input and the first input, as in Claim 5; and that the detector circuit includes a switch coupled to the resistor in series between the second input and the first input; and the power control circuit is capable of closing the switch in the first power mode. MIC2555 discloses a USB-OTG integrated circuit device (See Figure on Page 9) comprising: a set of pins (See Figure on Page 9 VBUS, ID, D+, and D-); and a detector circuit (See Figure on Page 9 ID Detector) that includes: a first input coupled to a first pin of the set of pins (See Figures on Pages 9 and 14 ID); wherein the detector circuit is capable of determining whether the first pin is shorted to ground (See Pages 13-14 Section ID Detector). MIC2555 further discloses that the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow (See Pages 13-14 Section ID Detector) from a voltage source (See Figure on Page 14 VBAT) to the first input (See Figure on Page 14 ID), as in Claim 4; that the detector circuit includes a resistor coupled between the voltage source and the first input (See Figure on Page 14 100k), as in Claim 5; and that the detector circuit includes a switch coupled to the resistor in series between the voltage source and the first input (See Figure on Page 14 switch connected between VBAT and resistor 100k); and the power control circuit is capable of closing the switch in a first (normal) power mode (See Pages 13-14 Section ID Detector), as in Claim 6. However, Elias and MIC2555 do not explicitly disclose that the voltage source used for the detector circuit is the first pin (VBUS). One of ordinary skill in the art would recognize that, as shown in Figure 5 of Elias and the Figure on Page 14 of MIC2555, there are a finite number of voltage sources available in Elias and MIC2555 to use as the voltage source (3.3V, 1.8V, 1.24V, VBAT, or VBUS), and the use of a particular voltage source does not affect the ability to detect whether the ID pin is shorted to ground.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Elias using the USB-OTG detector circuit of MIC2555, and trying the second pin (VBUS) as the power source for detecting that the first pin is shorted to ground, resulting in the invention of Claims 4, 5, and 6, because Elias is silent as to the particular structure of the detector circuit, and the simple substitution of the USB-OTG detector circuit of MIC 2555 as the USB-OTG detector circuit of Elias would have yielded the predictable result of allowing for the detection of both USB-OTG and non-USB OTG devices (See Pages 13-14 Section ID Detector); and because there are a finite number of voltages available in Elias and MIC2555 to use as the voltage source for detecting that the first pin is shorted to ground, and one of ordinary skill would have tried the second pin (VBUS) as the voltage source in an effort to provide an improved construction of the device of Elias and MIC2555, because one of ordinary skill in the art has good reason to try the known options within their technical grasp.
In reference to Claim 15, Elias discloses the limitations as applied to Claim 11 above. Elias further discloses that the detector circuit is coupled (See Figure 5 Number 412) to a second pin of the set of pins (See Figure 5 VBUS). Elias is silent as to the particular structure of the detector circuit, and does not explicitly disclose that the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow from the second pin to the first pin. MIC2555 discloses a USB-OTG integrated circuit device (See Figure on Page 9) comprising: a microcontroller (See Figure on Page 9) that includes: a set of pins (See Figure on Page 9 VBUS, ID, D+, and D-); a transceiver (See Figure on Page 9 Diff TX) coupled to a subset of the set of pins (See Figure on Page 9 D+ and D-); a detector circuit (See Figure on Page 9 ID Detector) coupled to a first pin of the set of pins (See Figures on Pages 9 and 14 ID), wherein the detector circuit is capable of: determining whether the first pin is shorted to ground (See Pages 13-14 Section ID Detector). MIC2555 further discloses that the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow (See Pages 13-14 Section ID Detector) from a voltage source (See Figure on Page 14 VBAT) to the first pin (See Figure on Page 14 ID). However, Elias and MIC2555 do not explicitly disclose that the voltage source used for the detector circuit is the first pin (VBUS). One of ordinary skill in the art would recognize that, as shown in Figure 5 of Elias and the Figure on Page 14 of MIC2555, there are a finite number of voltage sources available in Elias and MIC2555 to use as the voltage source (3.3V, 1.8V, 1.24V, VBAT, or VBUS), and the use of a particular voltage source does not affect the ability to detect whether the ID pin is shorted to ground.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Elias using the USB-OTG detector circuit of MIC2555, and trying the second pin (VBUS) as the power source for detecting that the first pin is shorted to ground, resulting in the invention of Claim 15, because Elias is silent as to the particular structure of the detector circuit, and the simple substitution of the USB-OTG detector circuit of MIC 2555 as the USB-OTG detector circuit of Elias would have yielded the predictable result of allowing for the detection of both USB-OTG and non-USB OTG devices (See Pages 13-14 Section ID Detector); and because there are a finite number of voltages available in Elias and MIC2555 to use as the voltage source for detecting that the first pin is shorted to ground, and one of ordinary skill would have tried the second pin (VBUS) as the voltage source in an effort to provide an improved construction of the device of Elias and MIC2555, because one of ordinary skill in the art has good reason to try the known options within their technical grasp.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elias and MIC2555.
In reference to Claim 16, Elias discloses a method comprising: operating an integrated circuit device (See Figure 5 Number 402 and 404 and Paragraphs 2 and 37) in a first power mode (See Paragraphs 15 and 38 [standby or sleep mode]); and in the first power mode: determining that a second pin (See Figure 5 Number 414) of the integrated circuit device is shorted to ground (See Paragraphs 28, 33, and 67 [USB-OTG connects the ID pin to ground when a micro-A plug is inserted]); and based on the second pin being shorted to ground, transitioning the integrated circuit device to a second power mode (See Paragraphs 28, 38-39, and 41) that is associated with a greater power consumption than the first power mode (See Paragraphs 15 and 28 [normal operating mode]), wherein the integrated circuit device includes a detector circuit (See Figure 5 Numbers 406, 408, and 502 and Paragraphs 28, 34, and 37-38) that includes: a first input (See Figure 5 Number 414) coupled to the first pin of a set of pins (See Figure 5 ID) and a second input (See Figure 5 Number 412) coupled to a second pin of the set of pins (See Figure 5 VBUS). Elias is silent as to the particular structure of the detector circuit, and does not explicitly disclose electrically coupling the first pin of the integrated circuit device to the second pin of the integrated circuit device; and determining that the second pin of the integrated circuit device is shorted to ground based on a current flow between the first pin and the second pin. MIC2555 discloses a USB-OTG integrated circuit device (See Figure on Page 9) comprising: a set of pins (See Figure on Page 9 VBUS, ID, D+, and D-); and a detector circuit (See Figure on Page 9 ID Detector) that includes: a first input coupled to a first pin of the set of pins (See Figures on Pages 9 and 14 ID); wherein the detector circuit is capable of determining whether the first pin is shorted to ground (See Pages 13-14 Section ID Detector). MIC2555 further discloses that the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow (See Pages 13-14 Section ID Detector) from a voltage source (See Figure on Page 14 VBAT) to the first input (See Figure on Page 14 ID). However, Elias and MIC2555 do not explicitly disclose that the voltage source used for the detector circuit is the first pin (VBUS). One of ordinary skill in the art would recognize that, as shown in Figure 5 of Elias and the Figure on Page 14 of MIC2555, there are a finite number of voltage sources available in Elias and MIC2555 to use as the voltage source (3.3V, 1.8V, 1.24V, VBAT, or VBUS), and the use of a particular voltage source does not affect the ability to detect whether the ID pin is shorted to ground.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Elias using the USB-OTG detector circuit of MIC2555, and trying the second pin (VBUS) as the power source for detecting that the first pin is shorted to ground, resulting in the invention of Claim 16, because Elias is silent as to the particular structure of the detector circuit, and the simple substitution of the USB-OTG detector circuit of MIC 2555 as the USB-OTG detector circuit of Elias would have yielded the predictable result of allowing for the detection of both USB-OTG and non-USB OTG devices (See Pages 13-14 Section ID Detector); and because there are a finite number of voltages available in Elias and MIC2555 to use as the voltage source for detecting that the first pin is shorted to ground, and one of ordinary skill would have tried the second pin (VBUS) as the voltage source in an effort to provide an improved construction of the device of Elias and MIC2555, because one of ordinary skill in the art has good reason to try the known options within their technical grasp.
In reference to Claim 17, Elias and MIC2555 disclose the limitations as applied to Claim 16 above. Elias further discloses that the first pin is a USB OTG (OTG) voltage supply pin (See Figure 5 and Paragraph 28). Elias further discloses that the second pin is a USB OTG ID pin (See Figure 5 and Paragraph 28).
In reference to Claim 18, Elias and MIC2555 disclose the limitations as applied to Claim 16 above. Elias further discloses that the transitioning of the integrated circuit device to the second power mode includes enabling (See Paragraphs 30, 32-33, 36, 43, and 66) a transceiver of the integrated circuit device (See Figure 5 Number 410 and Paragraphs 14, 20, 22, and 27).
In reference to Claim 19, Elias and MIC2555 disclose the limitations as applied to Claim 16 above. Elias further discloses that the transitioning of the integrated circuit device to the second power mode includes performing a boot process (See Paragraphs 32 and 36 [complete shutdown will necessarily require some sort of boot process when returning to the normal mode of operation]).
In reference to Claim 20, Elias and MIC2555 disclose the limitations as applied to Claim 19 above. Elias further discloses that the transitioning of the integrated circuit device to the second power mode includes enabling (See Paragraphs 32-33 and 66 [firmware and driver responds to power, resume, and/or attach signals to remove power gating to, and thus enable, the transceiver; gating power cuts off output of the power regulator, and thus removing gating enables the regulator within the broadest reasonable interpretation of the term]) a power regulator of the integrated circuit device (See Figure 5 Power Supply).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1 of U.S. Patent No. 12,321,306 to Nisarga et al (“Nisarga-306”).
Although the claims at issue are not identical, they are not patentably distinct from each other because the aforementioned claims of Nisarga-306 recite, in substantially equivalent form, all of the aforementioned claims of the instant application, as indicated below.
Claim 1 (Instant Application)
Claims 10 and 13 (Nisarga-306)
An integrated circuit device comprising:
[Claim 10] a microcontroller unit
a set of pins;
[Claim 10] a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
a power control circuit capable of causing the integrated circuit device to operate in a first power mode and a second power mode that is associated with greater power consumption than the first power mode;
[Claim 10] detecting that a microcontroller unit is to enter a low power mode…causing, using a flip flop of the power control circuit, a boot sequence to be initiated; and causing the microcontroller unit to exit the low power mode
and a detector circuit that includes: a first input coupled to a first pin of the set of pins;
[Claim 10] a detector of the microcontroller unit: detecting, using the detector and a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
and a first output coupled to the power control circuit;
[Claim 10] providing, using the detector, a signal that specifies whether the USB micro-A plug is inserted into the USB receptacle to a power control circuit
wherein the detector circuit is capable of, in the first power mode: determining whether the first pin is shorted to ground;
[Claim 13] detecting that the USB micro-A plug is inserted into the USB receptacle includes determining, using the resistor, that the USB ID pin is shorted to ground
and based on the first pin being shorted to ground, causing a transition from the first power mode to the second power mode.
[Claim 10] causing the microcontroller unit to exit the low power mode responsive to the signal specifying that the USB micro-A plug is inserted into the USB receptacle
Claim 2 (Instant Application)
Claim 10 (Nisarga-306)
the set of pins is capable of coupling to a Universal Serial Bus (USB) On The Go (OTG) receptacle; and the first pin is a USB OTG ID pin.
detecting, using the detector and a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin, whether a USB micro-A plug or a USB micro-B plug is inserted into a USB receptacle coupled to the microcontroller unit [a USB ID pin is a USB-OTG pin that is part of a USB-OTG receptacle]
Claim 3 (Instant Application)
Claim 10 (Nisarga-306)
the detector circuit includes a second input coupled to a second pin of the set of pins.
using the detector and a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
Claim 4 (Instant Application)
Claim 10 (Nisarga-306)
the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow from the second input to the first input.
a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin…the detecting is based on whether current flows from the VBUS pin through the resistor
Claim 5 (Instant Application)
Claim 10 (Nisarga-306)
the detector circuit includes a resistor coupled between the second input and the first input.
a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
Claim 6 (Instant Application)
Claim 2 (Nisarga-306)
the detector circuit includes a switch coupled to the resistor in series between the second input and the first input;
the detector circuit includes a switch coupled in series with the resistor between the voltage supply pin and the fourth pin,
and the power control circuit is capable of closing the switch in the first power mode.
and the controller is configured to close the switch responsive to the integrated circuit entering the first power mode.
Claim 7 (Instant Application)
Claims 10 and 13 (Nisarga-306)
the detector circuit is capable of determining whether the first pin is shorted to ground based on a voltage at the first input of the detector circuit.
[Claim 10] a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin…wherein the detecting is based on whether current flows from the VBUS pin through the resistor
[Claim 13] determining, using the resistor, that the USB ID pin is shorted to ground
Claim 8 (Instant Application)
Claim 10 (Nisarga-306)
a transceiver coupled to a subset of the set of pins, wherein the transition from the first power mode to the second power mode includes transitioning the transceiver from an inactive state to an active state.
causing the microcontroller unit to exit the low power mode…in which exiting the low power mode includes enabling the transceiver and the power regulator
Claim 9 (Instant Application)
Claim 10 (Nisarga-306)
a microcontroller that includes the power control circuit and the detector circuit, wherein the transition from the first power mode to the second power mode includes performing a boot process using the microcontroller.
a microcontroller unit…a detector…a power control circuit…based on the signal specifying that the USB micro-A plug is inserted into the USB receptacle, causing…a boot sequence to be initiated; and causing the microcontroller unit to exit the low power mode responsive to the signal specifying that the USB micro-A plug is inserted into the USB receptacle
Claim 10 (Instant Application)
Claim 10 (Nisarga-306)
a power regulator coupled to the power control circuit, wherein the transition from the first power mode to the second power mode includes enabling the power regulator.
exiting the low power mode includes enabling the transceiver and the power regulator.
Claim 11 (Instant Application)
Claims 10 and 13 (Nisarga-306)
An integrated circuit device comprising: a microcontroller that includes:
[Claim 10] a microcontroller unit
a power control circuit capable of causing the microcontroller to operate in a first mode and a second mode;
[Claim 10] detecting that a microcontroller unit is to enter a low power mode…causing, using a flip flop of the power control circuit, a boot sequence to be initiated; and causing the microcontroller unit to exit the low power mode
a set of pins;
[Claim 10] a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
a transceiver coupled to a subset of the set of pins;
[Claim 10] a transceiver
a detector circuit coupled to the power control circuit and to a first pin of the set of pins,
[Claim 10] a detector of the microcontroller unit: detecting, using the detector and a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin… providing, using the detector, a signal that specifies whether the USB micro-A plug is inserted into the USB receptacle to a power control circuit
wherein the detector circuit is capable of, in the first mode: determining whether the first pin is shorted to ground;
[Claim 13] detecting that the USB micro-A plug is inserted into the USB receptacle includes determining, using the resistor, that the USB ID pin is shorted to ground
and based on the first pin being shorted to ground, cause the power control circuit to cause a transition from the first mode to the second mode.
[Claim 10] causing the microcontroller unit to exit the low power mode responsive to the signal specifying that the USB micro-A plug is inserted into the USB receptacle
Claim 12 (Instant Application)
Claim 10 (Nisarga-306)
the transceiver is enabled in the second mode and is not enabled in the first mode.
in response to detecting that the microcontroller unit is to enter the low power mode: disabling a transceiver…exiting the low power mode includes enabling the transceiver
Claim 13 (Instant Application)
Claim 12 (Nisarga-306)
the second mode is associated with operation of the transceiver as a Universal Serial Bus (USB) host.
upon receiving the signal from the detector, initializing operation of the microcontroller unit as a USB host device
Claim 14 (Instant Application)
Claim 10 (Nisarga-306)
the first pin is a USB On The Go (OTG) ID pin
a USB identification (ID) pin [a USB ID pin is a USB-OTG pin that is part of a USB-OTG receptacle]
Claim 15 (Instant Application)
Claim 10 (Nisarga-306)
the detector circuit is coupled to a second pin of the set of pins;
using the detector and a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
and the detector circuit is capable of determining whether the first pin is shorted to ground based on current flow from the second pin to the first pin.
a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin…the detecting is based on whether current flows from the VBUS pin through the resistor
Claim 16 (Instant Application)
Claims 10 and 13 (Nisarga-306)
A method comprising: operating an integrated circuit device in a first power mode;
[Claim 10] detecting that a microcontroller unit is to enter a low power mode
and in the first power mode: electrically coupling a first pin of the integrated circuit device to a second pin of the integrated circuit device;
[Claim 10] a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin
determining that the second pin of the integrated circuit device is shorted to ground based on a current flow between the first pin and the second pin;
[Claim 10] a resistor coupled between a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin…the detecting is based on whether current flows from the VBUS pin through the resistor
[Claim 13] detecting that the USB micro-A plug is inserted into the USB receptacle includes determining, using the resistor, that the USB ID pin is shorted to ground
and based on the second pin being shorted to ground, transitioning the integrated circuit device to a second power mode that is associated with a greater power consumption than the first power mode.
[Claim 10] based on the signal specifying that the USB micro-A plug is inserted into the USB receptacle, causing…causing the microcontroller unit to exit the low power mode responsive to the signal specifying that the USB micro-A plug is inserted into the USB receptacle
Claim 17 (Instant Application)
Claim 10 (Nisarga-306)
the first pin is a Universal Serial Bus (USB) On The Go (OTG) voltage supply pin; and the second pin is a USB OTG ID pin.
a Universal Serial Bus (USB) VBUS pin and a USB identification (ID) pin [a USB ID pin is a USB-OTG pin that is part of a USB-OTG receptacle; thus, the VBUS pin of the interface must be a USB OTG voltage supply pin]
Claim 18 (Instant Application)
Claim 10 (Nisarga-306)
the transitioning of the integrated circuit device to the second power mode includes enabling a transceiver of the integrated circuit device.
causing the microcontroller unit to exit the low power mode…in which exiting the low power mode includes enabling the transceiver and the power regulator
Claim 19 (Instant Application)
Claim 10 (Nisarga-306)
the transitioning of the integrated circuit device to the second power mode includes performing a boot process.
based on the signal specifying that the USB micro-A plug is inserted into the USB receptacle, causing…a boot sequence to be initiated; and causing the microcontroller unit to exit the low power mode responsive to the signal specifying that the USB micro-A plug is inserted into the USB receptacle
Claim 20 (Instant Application)
Claim 10 (Nisarga-306)
the transitioning of the integrated circuit device to the second power mode includes enabling a power regulator of the integrated circuit device.
exiting the low power mode includes enabling the transceiver and the power regulator.
Claim(s) 1-2, 7-8, and 11-14 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 9, and 12 of U.S. Patent No. 10,545,908 to Nisarga et al (“Nisarga-908”).
Although the claims at issue are not identical, they are not patentably distinct from each other because the aforementioned claims of Nisarga-908recite, in substantially equivalent form, all of the aforementioned claims of the instant application, as indicated below.
Claim 1 (Instant Application)
Claims 1 and 9 (Nisarga-908)
An integrated circuit device comprising:
[Claim 1] An integrated circuit comprising:
a set of pins;
[Claim 1] a USB receptacle having multiple pinouts
a power control circuit capable of causing the integrated circuit device to operate in a first power mode and a second power mode that is associated with greater power consumption than the first power mode;
[Claim 1] power control module configured to: disable the transceiver and the power regulator in response to the detection that the integrated circuit is entering the low power mode…and cause the integrated circuit to exit the low power mode
and a detector circuit that includes: a first input coupled to a first pin of the set of pins;
[Claim 1] the detector circuit is configured to provide the indication to the power control module in response to the particular pinout receiving the first voltage and not in response to the particular pinout receiving the second voltage
and a first output coupled to the power control circuit;
[Claim 1] the power control module configured to…receive, from the detection circuit, an indication in response to the detector circuit detecting that the USB plug is inserted into the USB receptacle of the microcontroller unit
wherein the detector circuit is capable of, in the first power mode: determining whether the first pin is shorted to ground;
[Claim 1] wherein the detector circuit is configured to provide the indication to the power control module in response to the particular pinout receiving the first voltage
[Claim 9] wherein the first voltage is a ground voltage
and based on the first pin being shorted to ground, causing a transition from the first power mode to the second power mode.
[Claim 1] cause the integrated circuit to exit the low power mode when the power control module receives the indication
Claim 2 (Instant Application)
Claim 9 (Nisarga-908)
the set of pins is capable of coupling to a Universal Serial Bus (USB) On The Go (OTG) receptacle; and the first pin is a USB OTG ID pin.
the particular pinout is an ID pinout [a USB ID pin is a USB-OTG pin that is part of a USB-OTG receptacle]
Claim 7 (Instant Application)
Claim 9 (Nisarga-306)
the detector circuit is capable of determining whether the first pin is shorted to ground based on a voltage at the first input of the detector circuit.
[Claim 9] the first voltage is a ground voltage and the particular pinout is an ID pinout
Claim 8 (Instant Application)
Claim 12 (Nisarga-908)
a transceiver coupled to a subset of the set of pins, wherein the transition from the first power mode to the second power mode includes transitioning the transceiver from an inactive state to an active state.
upon detection of the indication that the USB micro-A plug is inserted into the USB receptacle: enabling the transceiver of the USB PHY circuit
Claim 11 (Instant Application)
Claims 1 and 9 (Nisarga-908)
An integrated circuit device comprising: a microcontroller that includes:
[Claim 1] An integrated circuit comprising…the microcontroller unit
a power control circuit capable of causing the microcontroller to operate in a first mode and a second mode;
[Claim 1] power control module configured to: disable the transceiver and the power regulator in response to the detection that the integrated circuit is entering the low power mode…and cause the integrated circuit to exit the low power mode
a set of pins;
[Claim 1] a USB receptacle having multiple pinouts
a transceiver coupled to a subset of the set of pins;
[Claim 1] a transceiver
a detector circuit coupled to the power control circuit and to a first pin of the set of pins,
[Claim 1] the detector circuit is configured to provide the indication to the power control module in response to the particular pinout receiving the first voltage and not in response to the particular pinout receiving the second voltage
wherein the detector circuit is capable of, in the first mode: determining whether the first pin is shorted to ground;
[Claim 1] wherein the detector circuit is configured to provide the indication to the power control module in response to the particular pinout receiving the first voltage
[Claim 9] wherein the first voltage is a ground voltage
and based on the first pin being shorted to ground, cause the power control circuit to cause a transition from the first mode to the second mode.
[Claim 1] cause the integrated circuit to exit the low power mode when the power control module receives the indication
Claim 12 (Instant Application)
Claim 1 (Nisarga-908)
the transceiver is enabled in the second mode and is not enabled in the first mode.
the power control module configured to: disable the transceiver and the power regulator in response to the detection that the integrated circuit is entering the low power mode
Claim 13 (Instant Application)
Claim 12 (Nisarga-908)
the second mode is associated with operation of the transceiver as a Universal Serial Bus (USB) host.
initializing operation of the microcontroller unit as a USB host device
Claim 14 (Instant Application)
Claim 9 (Nisarga-908)
the first pin is a USB On The Go (OTG) ID pin
wherein the first voltage is a ground voltage and the particular pinout is an ID pinout
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2 June 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Conclusion
The art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Transition Existing Products from USB 2.0 OTG to USB Type-CTM” by Michael Campbell, cited in the parent application and submitted on the IDS, provides evidence of various features necessarily present in USB-OTG.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
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