Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Applicant cites multiple parent applications with respect to priority and incorporation by reference. The disclosure of the invention in the parent applications and in the instant application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
Only applications 17/360646 and 16/384537 provide adequate support or enablement (describing the claimed unprotected and protected pipeline modes) in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for the claims of this application. Accordingly, the present claims are only entitled to the benefit of the earliest filing date of the 16/384537 application, filed April 15, 2019.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tatge, US Patent Application Publication 2009/0049280 (hereinafter Tatge) in view of Joyce et al., US Patent 7,805,592 (hereinafter Joyce), further in view of Egger et al., US Patent Application Publication 2010/0211759 (hereinafter Egger).
Regarding claim 1, Tatge teaches:
An integrated circuit comprising: a processor pipeline capable of operating in an unprotected mode and a protected mode (see e.g. fig. 1, 2, para. [0021], [0030]); and pipeline control circuitry coupled to the processor pipeline and capable of causing the processor pipeline to: in a second configuration, permit a second instruction initiated in the unprotected mode to complete in response to a change from the unprotected mode to the protected mode by completing the second instruction to produce a second result and writing the second result (see e.g. para. [0043-4], capable of causing the processor pipeline to permit instructions to complete).
Tatge fails to explicitly teach in a first configuration, annul a first instruction initiated in the unprotected mode in response to a change from the unprotected mode to the protected mode.
Joyce teaches squashing an instruction as indicated by resolving an instruction such as an “rv” instruction to change pipeline modes (see e.g. col. 8 lines 24-47, col. 12 lines 5-22, an rv instruction causes the processing pipeline to change from VLIW to scalar mode).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tatge and Joyce to in a first configuration, annul a first instruction initiated in the unprotected mode in response to a change from the unprotected mode to the protected mode. This would have ensured that unwanted instructions were not committed, thereby avoiding errors.
Tatge in view of Joyce fails to explicitly teach annulling by completing the first instruction to produce a first result and discarding the first result.
Egger teaches that based on a status value, an instruction is annulled by completing the instruction and discarding the result (see e.g. para. [0058], execution results are written or discarded depending on the predicate value).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tatge, Joyce, and Egger to perform annulling by completing the first instruction to produce a first result and discarding the first result. This would have provided additional flexibility in how to ensure an undesired instruction result was not committed, and would have been beneficial by reducing the need for additional steps such as to insert NOP instructions or disable functional units.
Regarding claim 2, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 1, wherein the pipeline control circuitry is capable of determining whether to stall or permit a third instruction to begin execution in the protected mode prior to the completing of the second instruction based on whether the second instruction and the third instruction utilize a location in common (see e.g. Tatge para. [0037-40], a determination of whether to stall is based on a data hazard between instructions).
Regarding claim 3, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 1, wherein the pipeline control circuitry is capable of causing the processor pipeline to change from the unprotected mode to the protected mode based on a processor instruction (see e.g. Tatge fig. 6, para. [0042-4], a directive instruction causes the pipeline to operate in a specified mode).
Regarding claim 4, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 3, wherein the pipeline control circuitry is capable of determining whether to operate in the first configuration or the second configuration based on the processor instruction (see e.g. Tatge fig. 6, para. [0042-4]).
Regarding claim 5, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 3, wherein the processor instruction is associated with a loop early exit (see e.g. Joyce col. 8 lines 44-47).
Claims 10-14 are rejected for reasons corresponding to those given above for claims 1-5.
Claims 16-20 are rejected for reasons corresponding to those given above for claims 1-5.
Claims 6, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tatge in view of Joyce and Egger, further in view of Granston et al., US Patent Application Publication 2002/0112228 (hereinafter Granston).
Regarding claim 6, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 3.
Tatge in view of Joyce and Egger fails to explicitly teach wherein the processor instruction is associated with an epilog collapse of a loop.
Granston teaches instructions associated with an epilog collapse of a loop (see e.g. para. [0012], [0041]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tatge, Joyce, Egger and Granston such that the processor instruction is associated with an epilog collapse of a loop. This would have provided an advantage of reducing code expansion by rolling some or all of the epilog back into a kernel (see Granston para. [0012]).
Claim 15 is rejected for reasons corresponding to those given above for claim 6.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tatge in view of Joyce and Egger, further in view of Hill et al., US Patent Application Publication 2007/0043930 (hereinafter Hill).
Regarding claim 7, Tatge in view of Joyce and Egger teaches or suggests:
The integrated circuit of claim 1.
Tatge in view of Joyce and Egger fails to explicitly teach further comprising a scoreboard coupled to the processor pipeline and capable of storing a value associated with an expected time of completion of the second instruction.
Hill teaches using a scoreboard capable of storing a value associated with an expected time of completion of an instruction (see e.g. para. [0048], a scoreboard stores a number of cycles that represents when an instruction’s results of execution will be available).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tatge, Joyce, Egger and Hill to include a scoreboard coupled to the processor pipeline and capable of storing a value associated with an expected time of completion of the second instruction. This would have provided an advantage such as discussed by Hill that “this approach can significantly improve the throughput of the data processing apparatus” (see e.g. para. [0019]).
Regarding claim 8, Tatge in view of Joyce, Egger, and Hill teaches or suggests:
The integrated circuit of claim 7, wherein the scoreboard includes a writeback queue and is capable of: based on an interrupt, storing an intermediate result of the second instruction in the writeback queue; and based on completion of the interrupt, restoring the intermediate result of the second instruction from the writeback queue to the processor pipeline based on the value associated with the expected time of completion of the second instruction (see e.g. Tatge para. [0048], Hill para. [0047-50]).
Regarding claim 9, Tatge in view of Joyce, Egger, and Hill teaches or suggests:
The integrated circuit of claim 7, wherein the scoreboard is capable of, in response to a change from the unprotected mode to the protected mode, adjusting the value associated with the expected time of completion of the second instruction to indicate completion of the second instruction prior to completion of the second instruction (see e.g. Tatge para. [0048], Hill para. [0047-50]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,048,513. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘513 patent and the instant application have substantially overlapping scope to their claims.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,029,997. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘997 patent and the instant application have substantially overlapping scope to their claims.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,321,750. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘750 patent and the instant application have substantially overlapping scope to their claims.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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